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CYPT2645KV18-250GCMB

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CYPT2645KV18-250GCMB
CYPT2645KV18-250GCMB

Product details

  • Currently planned availability until at least
    2033
  • Density
    144 MBit
  • ECC
    N
  • On-Die Termination
    Y
  • Architecture
    QDR-II+, ODT
  • Interfaces
    Parallel
  • Watchdog
    N
  • Device weight
    6152.8 mg
  • Data Width
    x 36
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Peak Reflow Temp
    220 °C
  • Family
    QDR-II+, ODT
  • Real Time Clock
    N
  • Lead Ball Finish
    Sn/Pb
  • Operating Temperature
    -55 °C to 125 °C
  • Operating Voltage
    1.7 V to 1.9 V
  • Frequency
    250 MHz
  • Organization (X x Y)
    4Mb x 36
  • Qualification
    Military
  • Read Latency (Cycles)
    2
OPN
CYPT2645KV18-250GCMB
製品ステータス active and preferred
インフィニオンパッケージ
パッケージ名 CCGA-165 (001-58969)
包装サイズ 1
包装形態 TRAY
水分レベル 1
モイスチャーパッキン NON DRY
鉛フリー No
ハロゲンフリー No
RoHS準拠 No
Infineon stock last updated:

製品ステータス
Active
インフィニオンパッケージ
パッケージ名 CCGA-165 (001-58969)
包装サイズ 1
包装形態 TRAY
水分レベル 1
モイスチャーパッキン NON DRY
鉛フリー
ハロゲンフリー
RoHS対応
Infineon’s 144Mb Quad Data Rate (QDR®)-II+, CYRS164x and CYRS264x series, are high performance, synchronous pipelined SRAMs designed with Infineon’s RADSTOP™ technology.  The 144Mb QDR®-II+ memories are available in x18/x36 and two-word/four-word data bus configurations, and optional on-die termination (ODT).  Our QDR®-II+ provides low latency and random memory access capability ideal for high speed cache applications. Infineon’s radiation hardened memories are QML-V certified, meeting the reliability and lifecycle demands of extreme environments. Our RADSTOPTM memory solutions enhance overall system computing limits while providing Size, Weight, and Power (SWaP) benefits and greater design flexibility. Infineon’s state-of-the art RADSTOP™ technology is radiation hardened through proprietary design and process hardening techniques.

機能

  • 144 Mb density, 4M x 36 with four-word burst mode
  • 250MHz max frequency / 36 Gbps throughput
  • Two independent unidirectional data ports for concurrent r/w transactions
  • Double Data Rate (DDR) port
  • Output impedance matching input (ZQ) matches the device outputs to system data bus impedance
  • Memory core bit-interleaving to eliminate multi-bit errors
  • On-die termination (ODT)
  • 1.5 V to 1.8 V HSTL I/O signaling standards
  • 1.7 V to 1.9 V operating voltage range
  • –55°C to +125°C military temperature grade
  • 165-ball ceramic CGA (CCGA)
  • PROTOTYPE
  • For flight  devices, order QML-V part number 5962R1821502VXF
  • Controller RTL IP cores with embedded EDAC are available for Xilinx and Microchip FPGAs
Dev kit available, to learn more:  QDR®-II+ mezzanine board (P/N: CYDK-QDRII-NODT)

用途

ドキュメント

デザイン リソース

開発者コミュニティ

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