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AN88889 Mitigating Single-Event Upsets Using Infineon 65-nm Asynchronous SRAM (Japanese)

This application note introduces the Error Correcting Code (ECC) feature of Infineon 65-nm 16-Mbit Asynchronous SRAMs. It explains major causes of single-event upsets in systems and how they are mitigated conventionally.

• 824.18 KB
• 2016/05/12