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AURIX-XILINX-FPGA-LINK

About

About Optimized AURIX™ - XILINX FPGA Link

Infineon Technologies AG, Xilinx, Inc. and Xylon, d.o.o. cooperate for more flexibility in using safety microcontrollers in automotive and industrial applications. The new IP-Core of Xylon enables high-speed communication between microcontrollers of Infineon's AURIX family (TC2xx and TC3xx) and Xilinx SoC (System-on-Chip), MPSoC (MultiProcessor SoC) and FPGA (Field Programmable Gate Arrays) devices via the Infineon High Speed Serial Link (HSSL). This serial link supports baud rates of up to 320 Mbaud at a net payload data-rate of up to 84%.

The new IP core will allow system developers to combine functional safety and security provided by AURIX™ with the wide range of functional possibilities brought to the table by the Xilinx devices. Linked devices can access and control each other’s internal and connected resources through the HSSL.

Features
  • Currently supports Xilinx 7 Series and Zynq-7000 SoC device families
  • Support for Xilinx UltraScale, UltraScale+ FPGA devices, and Zynq UltraScale+ MPSoC planned for the near future.
  • HSSL slave device
  • Up to 320 Mbaud/s baud rate
  • ARM AMBA AXI4-Lite bus protocol compliant as a slave device
  • ARM AMBA AXI4 bus protocol compliant as a master device
  • 3.25 GB of addressable space covers accesses to:

           -  FPGA fabric registers and RAM

           -  PS section register space and OCM

           -  On-board linearly addressable FLASH devices

           -  On-board DDR memory

About Optimized AURIX™ - XILINX FPGA Link

Infineon Technologies AG, Xilinx, Inc. and Xylon, d.o.o. cooperate for more flexibility in using safety microcontrollers in automotive and industrial applications. The new IP-Core of Xylon enables high-speed communication between microcontrollers of Infineon's AURIX family (TC2xx and TC3xx) and Xilinx SoC (System-on-Chip), MPSoC (MultiProcessor SoC) and FPGA (Field Programmable Gate Arrays) devices via the Infineon High Speed Serial Link (HSSL). This serial link supports baud rates of up to 320 Mbaud at a net payload data-rate of up to 84%.

The new IP core will allow system developers to combine functional safety and security provided by AURIX™ with the wide range of functional possibilities brought to the table by the Xilinx devices. Linked devices can access and control each other’s internal and connected resources through the HSSL.

Features
  • Currently supports Xilinx 7 Series and Zynq-7000 SoC device families
  • Support for Xilinx UltraScale, UltraScale+ FPGA devices, and Zynq UltraScale+ MPSoC planned for the near future.
  • HSSL slave device
  • Up to 320 Mbaud/s baud rate
  • ARM AMBA AXI4-Lite bus protocol compliant as a slave device
  • ARM AMBA AXI4 bus protocol compliant as a master device
  • 3.25 GB of addressable space covers accesses to:

           -  FPGA fabric registers and RAM

           -  PS section register space and OCM

           -  On-board linearly addressable FLASH devices

           -  On-board DDR memory

Documents

Documents

デザイン リソース

Image gallery

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