CY7S1049GE30-10VXIT
Active and preferred
RoHS Compliant
Lead-free

CY7S1049GE30-10VXIT

Datasheet
package

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CY7S1049GE30-10VXIT
CY7S1049GE30-10VXIT
Datasheet


Product details

  • Density
    4 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    512K x 8
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Speed
    10 ns

Recommended
OPN
CY7S1049GE30-10VXIT
Product Status active and preferred
Infineon Package
PG-SOJ-36
Package Name SOJ-36 (51-85090)
Packing Size 500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-SOJ-36
Package Name SOJ-36 (51-85090)
Packing Size 500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
CY7S1049GE30-10VXIT is a 4-Mbit (512K × 8) asynchronous SRAM with embedded ECC and an ERR pin for single-bit error detect/correct indication. It supports 10 ns access (tAA) at 2.2 V to 3.6 V, operates from -40°C to +85°C, and offers CMOS standby ISB2 up to 8 mA. Deep-Sleep disables normal operation for data retention with IDS up to 15 µA. The -VXIT option is a 36-pin SOJ, tape-and-reel.

Features

  • 4-Mbit SRAM, 512K × 8 org
  • 10 ns / 15 ns address access
  • Read cycle time tRC 10/15 ns
  • OE to data valid tDOE 4.5/8 ns
  • Embedded ECC corrects 1-bit errors
  • Deep-Sleep current IDS max 15 µA
  • DS to Deep-Sleep tDS max 1 ms
  • Wake to access tDSCA 300 µs
  • Data retention at VDR = 1.0 V
  • TTL-compatible inputs and outputs
  • Operating temp –40°C to +85°C

Benefits

  • Fast reads reduce memory latency
  • Quick OE timing speeds bus turns
  • ECC reduces silent data corruption
  • 15 µA Deep-Sleep cuts power draw
  • DS pin enables on-demand sleep
  • 300 µs wake supports fast resume
  • 1.0 V retention saves backup power
  • TTL levels ease legacy interfaces
  • –40°C to +85°C improves robustness
  • Predictable timing eases design

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