Flash+RAM MCP solutions

Flash and RAM in a single package for ease of design

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Overview

For systems that require flash and RAM memory, Infineon multi-chip package (MCP) solutions simplify overall system design. By integrating both memories into a single package, Infineon MCP products decrease the BOM, lower the pin count, and reduce the PCB size and layer requirements. Infineon MCP solutions offer a single, space-saving package with no compromise in performance and quality.

Key Features

  • Flash and RAM in a single package
  • Standard pinouts
  • Common footprints
  • xSPI-compliant interfaces
  • Smaller, simpler PCB
  • Lower pin count
  • Fewer PCB layers
  • Easy migration
  • Fast time to market

Products

About

Flash+RAM MCP Gen 2 improves on HYPERBUS™ MCP (the prior generation) with increased performance and reliability. MCP Gen 2 upgrades from HYPERFLASH™ to SEMPER™ NOR flash and from HYPERRAM™ 1.0 to HYPERRAM™ 2.0. MCP Gen 2 also expands chipset support with the addition of an octal interface option.

Compared to separate flash and RAM chips, Infineon MCPs simplify PCB complexity in two ways:

  1. Combining two chips in one reduces the BOM.
  2. Going from a wide, parallel DDR SDRAM interface to a shared serial interface reduces the number of traces.

The result is a smaller PCB with fewer layers. Infineon also enables backward and forward compatibility with common packages. SEMPER™ NOR flash, HYPERFLASH™, HYPERRAM™, and MCP solutions all share a consistent footprint and pinout. This common design enables a single board to support a variety of memories without major redesign and provides the flexibility to easily expand from flash or RAM to a system that supports both.

The JEDEC xSPI standard (JESD251) was adopted in 2017 to promote compatibility and interoperability between memory, chipsets, and other devices. Infineon’s Flash+RAM MCP Gen 2 is offered in Octal (JEDEC xSPI Profile 1) and HYPERBUS™ (JEDEC xSPI Profile 2) interface options. Both offer the maximum x8 performance of 400 MBps as specified by the standard.

SEMPER™ Solutions Hub provides all the necessary building blocks to successfully integrate SEMPER™ NOR flash into your design, including:

  • Software development kits
  • Hardware development platforms
  • Support for a variety of development environments
  • Linux/U-Boot support

Visit the hub now to gain time-to-market advantage.

Flash+RAM MCP Gen 2 improves on HYPERBUS™ MCP (the prior generation) with increased performance and reliability. MCP Gen 2 upgrades from HYPERFLASH™ to SEMPER™ NOR flash and from HYPERRAM™ 1.0 to HYPERRAM™ 2.0. MCP Gen 2 also expands chipset support with the addition of an octal interface option.

Compared to separate flash and RAM chips, Infineon MCPs simplify PCB complexity in two ways:

  1. Combining two chips in one reduces the BOM.
  2. Going from a wide, parallel DDR SDRAM interface to a shared serial interface reduces the number of traces.

The result is a smaller PCB with fewer layers. Infineon also enables backward and forward compatibility with common packages. SEMPER™ NOR flash, HYPERFLASH™, HYPERRAM™, and MCP solutions all share a consistent footprint and pinout. This common design enables a single board to support a variety of memories without major redesign and provides the flexibility to easily expand from flash or RAM to a system that supports both.

The JEDEC xSPI standard (JESD251) was adopted in 2017 to promote compatibility and interoperability between memory, chipsets, and other devices. Infineon’s Flash+RAM MCP Gen 2 is offered in Octal (JEDEC xSPI Profile 1) and HYPERBUS™ (JEDEC xSPI Profile 2) interface options. Both offer the maximum x8 performance of 400 MBps as specified by the standard.

SEMPER™ Solutions Hub provides all the necessary building blocks to successfully integrate SEMPER™ NOR flash into your design, including:

  • Software development kits
  • Hardware development platforms
  • Support for a variety of development environments
  • Linux/U-Boot support

Visit the hub now to gain time-to-market advantage.

Documents

Design resources

Developer community

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