EZ-PD™ CCG7S Automotive single-port USB-C PD solution with a DC-DC controller

EZ-PD™ CCG7S Automotive USB single-port USB-C Power Delivery solution with a buck-boost controller

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Overview

EZ-PD™ CCG7S is a single-port USB-C Power Delivery (PD) solution with an integrated buck-boost controller. It complies with the latest USB Type-C and PD specifications (ver. 3.1) and is targeted at automotive charger applications such as head unit chargers, rear seat chargers, and rear seat entertainment systems. Integrations offered by EZ-PD™ CCG7S reduce the BOM and provide an optimized footprint for solutions of up to 100 W of power output.

Key Features

  • Supports USB PD 3.1 and PPS mode
  • Configurable resistors Rp and Rd
  • Gate driver for VBUS provider NFET
  • 100 mW VCONN power supply & control
  • 1x buck-boost controller
  • 1 legacy/proprietary charging block
  • Supports QC, 2.4 A, AFC, BC 1.2
  • OVP, OCP, UVP, VBUS-to-CC, UVLO
  • 32-bit 48 MHz Arm® Cortex®-M0
  • 128 KB flash, 16 KB SRAM, 32 KB ROM
  • Up to 14 GPIOs, 3x SCBs
  • Automotive temperature range

Products

About

EZ-PD™ CCG7S MCU subsystem

The Arm® Cortex®-M0 processor embedded in EZ-PD™ CCG7S is a 32-bit MCU specifically designed for efficient low-power operation through the implementation of extensive clock gating techniques. The subsystem integrates an interrupt controller known as the NVIC block and a wakeup interrupt controller (WIC) capable of waking the processor from Deep Sleep mode. In terms of memory, EZ-PD™ CCG7S devices are equipped with 128 KB flash and 32 KB ROM for non-volatile storage. The ROM is primarily utilized to store libraries for authentication and device drivers, such as I2C, SPI, and others. This allocation spares the flash memory for customer features and enables the firmware upgrades necessary to comply with the latest USB Power Delivery specifications and application requirements. Additionally, there is a 16 KB RAM that is utilized under software control to store temporary statuses of system variables and parameters. To facilitate booting and configuration processes, a supervisory ROM containing boot and configuration routines is included in the device.

EZ-PD™ CCG7S USB PD subsystem

The USB PD subsystem provides the interface to the Type-C USB port. The USB PD physical layer consists of both a transmitter and receiver, which communicate BMC-encoded data over the CC channel, per the PD 3.1 standard. All communication is half-duplex. To minimize communication errors, the physical layer (PHY) implements collision avoidance techniques. The USB PD block incorporates all termination resistors (Rp and Rd) and their respective switches as mandated by the USB PD specification. EZ-PD™ CCG7S family along with the accompanying firmware is fully compliant with revision 3.1 of the USB Power Delivery specification and supports programmable power supply (PPS) operation at all valid voltages from 3.3 V to 21 V.

  • Reduced BOM
  • Reduced design cycle
  • SDK for configurable value-added features
  • Programmable power supply (PPS)
  • Dynamic load sharing to distribute power between ports
  • Granular output power throttling based on VBATT and module temperature
  • Black box to store critical Type-C port parameters
  • Alternate mode support for rear seat entertainment systems
  • Authenticated field firmware upgradability
Why choose EZ-PD™ CCG7S
  • Reduced BOM
  • Reduced design cycle
  • SDK for configurable value-added features
  • Programmable power supply (PPS)
  • Dynamic load sharing to distribute power between ports
  • Granular output power throttling based on VBATT and module temperature
  • Black box to store critical Type-C port parameters
  • Alternate mode support for rear seat entertainment systems
  • Authenticated field firmware upgradability

EZ-PD™ CCG7S MCU subsystem

The Arm® Cortex®-M0 processor embedded in EZ-PD™ CCG7S is a 32-bit MCU specifically designed for efficient low-power operation through the implementation of extensive clock gating techniques. The subsystem integrates an interrupt controller known as the NVIC block and a wakeup interrupt controller (WIC) capable of waking the processor from Deep Sleep mode. In terms of memory, EZ-PD™ CCG7S devices are equipped with 128 KB flash and 32 KB ROM for non-volatile storage. The ROM is primarily utilized to store libraries for authentication and device drivers, such as I2C, SPI, and others. This allocation spares the flash memory for customer features and enables the firmware upgrades necessary to comply with the latest USB Power Delivery specifications and application requirements. Additionally, there is a 16 KB RAM that is utilized under software control to store temporary statuses of system variables and parameters. To facilitate booting and configuration processes, a supervisory ROM containing boot and configuration routines is included in the device.

EZ-PD™ CCG7S USB PD subsystem

The USB PD subsystem provides the interface to the Type-C USB port. The USB PD physical layer consists of both a transmitter and receiver, which communicate BMC-encoded data over the CC channel, per the PD 3.1 standard. All communication is half-duplex. To minimize communication errors, the physical layer (PHY) implements collision avoidance techniques. The USB PD block incorporates all termination resistors (Rp and Rd) and their respective switches as mandated by the USB PD specification. EZ-PD™ CCG7S family along with the accompanying firmware is fully compliant with revision 3.1 of the USB Power Delivery specification and supports programmable power supply (PPS) operation at all valid voltages from 3.3 V to 21 V.

  • Reduced BOM
  • Reduced design cycle
  • SDK for configurable value-added features
  • Programmable power supply (PPS)
  • Dynamic load sharing to distribute power between ports
  • Granular output power throttling based on VBATT and module temperature
  • Black box to store critical Type-C port parameters
  • Alternate mode support for rear seat entertainment systems
  • Authenticated field firmware upgradability

Why choose EZ-PD™ CCG7S
  • Reduced BOM
  • Reduced design cycle
  • SDK for configurable value-added features
  • Programmable power supply (PPS)
  • Dynamic load sharing to distribute power between ports
  • Granular output power throttling based on VBATT and module temperature
  • Black box to store critical Type-C port parameters
  • Alternate mode support for rear seat entertainment systems
  • Authenticated field firmware upgradability

Documents

Documents

Design resources

Developer community

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