EZ-PD™ ACG1F one-port USB-C controller

Single-port USB-C controller with integrated VBUS load switch

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Overview

EZ-PD™ ACG1F (Type-A to Type-C Generation 1 FET) is a single-port USB-C controller which complies with the latest USB-C specifications and is targeted at systems that need to convert legacy Type-A data ports to Type-C data ports. It integrates a 16-bit flash, 32-bit Arm® Cortex®-M0 processor, a Type-C controller (without Power Delivery), and a VBUS load switch (5 V/3 A), offering a complete USB-C control solution for notebooks and desktops.

Key Features

  • USB Type-C controller
  • 2x VCONN FET with OCP
  • VBUS load switch support
  • 5 V/3 A VBUS NFET
  • RDS(on) of load switch: 45 mΩ (typ)
  • Slew rate control turn-ON via VBUS
  • Configurable VBUS OVP, OCP, and RCP
  • Over-temperature thermal shutdown
  • VBUS to CC short protection
  • Supports USB-C UCSI over I2C
  • 32-bit MCU, 16 MHz Arm® Cortex®-M0
  • 16 KB flash, 4 KB SRAM, 32 KB SROM

Products

About

EZ-PD™ ACG1F USB-C subsystem

USB-C subsystem encompasses the interface to the Type-C USB port and includes the USB PD physical layer, VCONN FETs, ADC, undervoltage, overvoltage, reverse-current protection on VBUS, high-side current sense amplifier for VBUS with OCP and short-circuit protection (SCP), VBUS discharge, gate driver for VBUS NFET, and charger detection capability. The USB PD physical layer comprises of two Deep Sleep comparators responsible for detecting Type-C attachment and detachment, CC line activity events, and determining the voltage range on the selected CC line. Furthermore, this block includes Rp termination and associated switches as mandated by the USB Type-C specification. The chip implements an undervoltage/overvoltage (UVOV) detection circuit for the VBUS supply, and VBUS current sensing through the VBUS path, both with programmable thresholds. EZ-PD™ ACG1F has an integrated VBUS provider load switch, which includes OVP, OCP, SCP, RCP protection, a high-side current sense amplifier, and the RCP circuitry. The chip also implements battery charger emulation (source) for USB BC v1.2, supporting high-voltage tolerant CC lines.

EZ-PD™ ACG1F MCU subsystem

EZ-PD™ ACG1F integrates an Arm® Cortex ®-M0 with a serial wire debug (SWD) interface as part of a 32-bit MCU subsystem which is optimized for low-power operation with extensive clock gating. For memory, the device integrates a 16 KB flash that contains the firmware implementing Type-C functionality and supports in-system firmware upgrade through the SWD or I2C interface. A part of the flash can be also used for storing device and system power parameters. The 32 KB SROM hosts boot and configuration routine and can be also used to store frequently used functionalities in the firmware. The 4 KB RAM is used under software control to store temporary status of system variables and parameters.

EZ-PD™ ACG1F power system

EZ-PD™ ACG1F operates using a single power supply input, VDDD, with a valid voltage range of 2.7 V to 5.5 V. Additionally, there is a V5V supply pin responsible for providing the VCONN supply to the Type-C connector. V5V operates between 4.85 V to 5.5 V and does not power the chip itself but solely supports operation within the mentioned range. The VDDD input supports operation between 2.7 V and 5.5 V. The device offers two distinct power modes: Active and Deep Sleep, of which transition is managed by the power system. Additionally, there is a separate power domain, VDDIO, specifically designed for the GPIOs. EZ-PD™ ACG1F includes two SCBs, which can each implement only an I2C, eight GPIOs in the 40-QFN package, and five GPIOs in 24-QFN, including the I2C and SWD pins, which can also be used as GPIOs.

EZ-PD™ ACG1F USB-C subsystem

USB-C subsystem encompasses the interface to the Type-C USB port and includes the USB PD physical layer, VCONN FETs, ADC, undervoltage, overvoltage, reverse-current protection on VBUS, high-side current sense amplifier for VBUS with OCP and short-circuit protection (SCP), VBUS discharge, gate driver for VBUS NFET, and charger detection capability. The USB PD physical layer comprises of two Deep Sleep comparators responsible for detecting Type-C attachment and detachment, CC line activity events, and determining the voltage range on the selected CC line. Furthermore, this block includes Rp termination and associated switches as mandated by the USB Type-C specification. The chip implements an undervoltage/overvoltage (UVOV) detection circuit for the VBUS supply, and VBUS current sensing through the VBUS path, both with programmable thresholds. EZ-PD™ ACG1F has an integrated VBUS provider load switch, which includes OVP, OCP, SCP, RCP protection, a high-side current sense amplifier, and the RCP circuitry. The chip also implements battery charger emulation (source) for USB BC v1.2, supporting high-voltage tolerant CC lines.

EZ-PD™ ACG1F MCU subsystem

EZ-PD™ ACG1F integrates an Arm® Cortex ®-M0 with a serial wire debug (SWD) interface as part of a 32-bit MCU subsystem which is optimized for low-power operation with extensive clock gating. For memory, the device integrates a 16 KB flash that contains the firmware implementing Type-C functionality and supports in-system firmware upgrade through the SWD or I2C interface. A part of the flash can be also used for storing device and system power parameters. The 32 KB SROM hosts boot and configuration routine and can be also used to store frequently used functionalities in the firmware. The 4 KB RAM is used under software control to store temporary status of system variables and parameters.

EZ-PD™ ACG1F power system

EZ-PD™ ACG1F operates using a single power supply input, VDDD, with a valid voltage range of 2.7 V to 5.5 V. Additionally, there is a V5V supply pin responsible for providing the VCONN supply to the Type-C connector. V5V operates between 4.85 V to 5.5 V and does not power the chip itself but solely supports operation within the mentioned range. The VDDD input supports operation between 2.7 V and 5.5 V. The device offers two distinct power modes: Active and Deep Sleep, of which transition is managed by the power system. Additionally, there is a separate power domain, VDDIO, specifically designed for the GPIOs. EZ-PD™ ACG1F includes two SCBs, which can each implement only an I2C, eight GPIOs in the 40-QFN package, and five GPIOs in 24-QFN, including the I2C and SWD pins, which can also be used as GPIOs.

Documents

Documents

Design resources

Developer community

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