AURIX™ - XILINX FPGA Link

Maximize performance with optimized AURIX™-XILINX FPGA link

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About

About optimized AURIX™ - XILINX FPGA Link

Infineon Technologies AG, Xilinx, Inc. and Xylon, d.o.o. cooperate for more flexibility in using safety microcontrollers in automotive and industrial applications. The new IP-Core of Xylon enables high-speed communication between microcontrollers of Infineon's AURIX family (TC2xx and TC3xx) and Xilinx SoC (System-on-Chip), MPSoC (MultiProcessor SoC) and FPGA (Field Programmable Gate Arrays) devices via the Infineon High Speed Serial Link (HSSL). This serial link supports baud rates of up to 320 Mbaud at a net payload data-rate of up to 84%.

The new IP core will allow system developers to combine functional safety and security provided by AURIX™ with the wide range of functional possibilities brought to the table by the Xilinx devices. Linked devices can access and control each other’s internal and connected resources through the HSSL.

Xylon HSSL IP Core Features
  • Currently supports Xilinx 7 Series and Zynq-7000 SoC device families
  • Support for Xilinx UltraScale, UltraScale+ FPGA devices, and Zynq UltraScale+ MPSoC planned for the near future.
  • HSSL slave device
  • Up to 320 Mbaud/s baud rate
  • ARM AMBA AXI4-Lite bus protocol compliant as a slave device
  • ARM AMBA AXI4 bus protocol compliant as a master device
  • 3.25 GB of addressable space covers accesses to:

           -  FPGA fabric registers and RAM

           -  PS section register space and OCM

           -  On-board linearly addressable FLASH devices

           -  On-board DDR memory

For development support, the partners offer the FPGA HSSL starter kit

Kit description 

The logiHSSL-ZU FPGA  HSSL Starter Kit designs provides system designers with everything they need to quickly interconnect the Infineon’s AURIX™ microcontrollers with the Xilinx All Programmable FPGA and SoC devices via the Infineon High Speed Serial Link (HSSL). Combinations of these devices solve the rising safety and performance requirements in emerging automotive and industrial designs.

Kit content 

  • Combines Infineon's AURIX™ microcontroller and Xilinx's UltraScale+ MPSoC programmable device
  • Integrates Infineon High Speed Serial Link (HSSL) optimized for Xilinx FPGA implementations
  • Includes complete reference design with the evaluation logiHSSL IP core
  • Design is prepared for Xilinx Vivado® Design Suite
  • Linked devices can access and control each other's resources
  • Complete hardware platform includes:
    - 1x Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit                           
    - 1x Infineon Aurix Evaluation Board Kit KIT_A2G_TC397_5V_TRB_S
    - 1x Xylon FMC board for cable connection
    - 1x FireWire cable
Zynq-7000 SoC Demo Design Example – Block Diagram
  • The HSSL IP core (HSSL #0) can access register sets of all SoC IP cores through the PS 7 AXI Interconnect
  • The HSSL control module can access internal HSCT, HSSL and BCU register space through the same AXI infrastructure
  • HSSL IP core can access PS register space and on-board memory through GP and HP AXI3 ports on PL-PS interface
  • Programmable logiCLK IP core changes clocking on the fly and enables HSSL IP core setup to the required baud rate
Documentation and technical Support

Infineon technical support

  1. Please register under myinfineon.com (hyperlink) with your company e-mail address
  2. Send login name to: AURIX@infineon.com
  3. Automated update service will be provided for new documents once you are registered
  4. Full registration process can take up to 24h to be completed (due to different time zones).
Xylon technical support
Step-by-step instructions to get registered

About optimized AURIX™ - XILINX FPGA Link

Infineon Technologies AG, Xilinx, Inc. and Xylon, d.o.o. cooperate for more flexibility in using safety microcontrollers in automotive and industrial applications. The new IP-Core of Xylon enables high-speed communication between microcontrollers of Infineon's AURIX family (TC2xx and TC3xx) and Xilinx SoC (System-on-Chip), MPSoC (MultiProcessor SoC) and FPGA (Field Programmable Gate Arrays) devices via the Infineon High Speed Serial Link (HSSL). This serial link supports baud rates of up to 320 Mbaud at a net payload data-rate of up to 84%.

The new IP core will allow system developers to combine functional safety and security provided by AURIX™ with the wide range of functional possibilities brought to the table by the Xilinx devices. Linked devices can access and control each other’s internal and connected resources through the HSSL.

Xylon HSSL IP Core Features
  • Currently supports Xilinx 7 Series and Zynq-7000 SoC device families
  • Support for Xilinx UltraScale, UltraScale+ FPGA devices, and Zynq UltraScale+ MPSoC planned for the near future.
  • HSSL slave device
  • Up to 320 Mbaud/s baud rate
  • ARM AMBA AXI4-Lite bus protocol compliant as a slave device
  • ARM AMBA AXI4 bus protocol compliant as a master device
  • 3.25 GB of addressable space covers accesses to:

           -  FPGA fabric registers and RAM

           -  PS section register space and OCM

           -  On-board linearly addressable FLASH devices

           -  On-board DDR memory

For development support, the partners offer the FPGA HSSL starter kit

Kit description 

The logiHSSL-ZU FPGA  HSSL Starter Kit designs provides system designers with everything they need to quickly interconnect the Infineon’s AURIX™ microcontrollers with the Xilinx All Programmable FPGA and SoC devices via the Infineon High Speed Serial Link (HSSL). Combinations of these devices solve the rising safety and performance requirements in emerging automotive and industrial designs.

Kit content 

  • Combines Infineon's AURIX™ microcontroller and Xilinx's UltraScale+ MPSoC programmable device
  • Integrates Infineon High Speed Serial Link (HSSL) optimized for Xilinx FPGA implementations
  • Includes complete reference design with the evaluation logiHSSL IP core
  • Design is prepared for Xilinx Vivado® Design Suite
  • Linked devices can access and control each other's resources
  • Complete hardware platform includes:
    - 1x Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit                           
    - 1x Infineon Aurix Evaluation Board Kit KIT_A2G_TC397_5V_TRB_S
    - 1x Xylon FMC board for cable connection
    - 1x FireWire cable

Zynq-7000 SoC Demo Design Example – Block Diagram
  • The HSSL IP core (HSSL #0) can access register sets of all SoC IP cores through the PS 7 AXI Interconnect
  • The HSSL control module can access internal HSCT, HSSL and BCU register space through the same AXI infrastructure
  • HSSL IP core can access PS register space and on-board memory through GP and HP AXI3 ports on PL-PS interface
  • Programmable logiCLK IP core changes clocking on the fly and enables HSSL IP core setup to the required baud rate

Documentation and technical Support

Infineon technical support

  1. Please register under myinfineon.com (hyperlink) with your company e-mail address
  2. Send login name to: AURIX@infineon.com
  3. Automated update service will be provided for new documents once you are registered
  4. Full registration process can take up to 24h to be completed (due to different time zones).
Xylon technical support
Step-by-step instructions to get registered

Image gallery

Demo-Kit-Xylon.png
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xylonblockdiagram-7000.png_477027362 xylonblockdiagram-7000.png_477027362 xylonblockdiagram-7000.png_477027362
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