CY7C1482BV33-200BZI
Active and preferred

CY7C1482BV33-200BZI

Datasheet
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CY7C1482BV33-200BZI
CY7C1482BV33-200BZI
Datasheet


Product details

  • Architecture
    Standard Sync, Pipeline SCD
  • Bank Switching
    N
  • Data Width
    x 18
  • Density
    72 MBit
  • ECC
    N
  • Family
    Standard Sync
  • Frequency
    200 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    4Mb x 18
  • Peak Reflow Temp
    220 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1

Recommended
OPN
CY7C1482BV33-200BZI
Product Status active and preferred
Infineon Package
P -BGA-165
Package Name FBGA-165 (51-85165)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant No
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
P -BGA-165
Package Name FBGA-165 (51-85165)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
CY7C1482BV33-200BZI is a 72-Mbit (4M × 18) pipelined synchronous SRAM with registered inputs/outputs for 3-1-1-1 burst accesses. It supports up to 200 MHz bus operation with a user-selectable 2-bit burst counter (interleaved or linear), byte writes, and asynchronous OE plus ZZ sleep. It runs from 3.135 V to 3.6 V core with 2.375 V to VDDQ I/O, in a 165-ball FBGA, Industrial -40 to 85°C.

Features

  • Bus operation up to 250 MHz
  • 3.0 ns max clock-to-output tCO
  • Registered I/O for pipelining
  • High-performance 3-1-1-1 access
  • 2-bit wraparound burst counter
  • Linear or interleaved burst (MODE)
  • ADSP/ADSC address strobes
  • ADV increments burst address
  • Byte write via BWE and BWX
  • Global write (GW) all bytes
  • Asynchronous OE tri-state control
  • ZZ sleep mode with data retention

Benefits

  • 250 MHz supports high throughput
  • 3.0 ns tCO lowers read latency
  • Pipelining boosts system clock rate
  • 3-1-1-1 speeds burst transfers
  • On-chip counter cuts external logic
  • Burst modes fit CPU bus types
  • ADSP/ADSC simplifies bus interfacing
  • ADV enables fast sequential fetches
  • Byte write reduces write bandwidth
  • Global write speeds full updates
  • Tri-state eases bus sharing
  • Sleep mode reduces idle power

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