CY7C1470V25-200BZI
Active and preferred

CY7C1470V25-200BZI

Datasheet
package
ea.
in stock

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CY7C1470V25-200BZI
CY7C1470V25-200BZI
ea.
Datasheet


Product details

  • Architecture
    NoBL, Pipeline
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    200 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.38 V to 2.63 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    220 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1

Recommended
OPN
CY7C1470V25-200BZI
Product Status active and preferred
Infineon Package
P -BGA-165
Package Name FBGA-165 (51-85165)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant No
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
P -BGA-165
Package Name FBGA-165 (51-85165)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
ea.
in stock
The CY7C1470V25-200BZI is a 72-Mbit (2M × 36) 2.5 V synchronous pipelined burst SRAM with No Bus Latency (NoBL) architecture. It supports 200 MHz bus operation with zero wait states and fully registered inputs/outputs, plus byte-write capability and linear or interleaved burst order. It operates from 2.375 V to 2.625 V over -40°C to +85°C and is offered in a 165-ball FBGA package.

Features

  • NoBL SRAM, zero wait-state R/W
  • 200 MHz synchronous pipelined bus
  • Fully registered inputs and outputs
  • 3.0 ns max clock-to-output (tCO)
  • Burst counter: up to 4 transfers
  • Linear or interleaved burst order
  • Byte write with BW[x] selects
  • 2.5 V VDD supply (2.375-2.625 V)
  • 2.5 V VDDQ I/O supply (2.375-VDD)
  • Clock enable (CEN) stalls clock
  • Asynchronous OE for tri-state control
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • No wait states boost bandwidth
  • 200 MHz supports fast SRAM buses
  • Registered I/O eases timing closure
  • 3.0 ns tCO cuts read latency
  • 4-beat bursts reduce addr toggles
  • Burst order fits cache line needs
  • Byte writes simplify RMW updates
  • 2.5 V core lowers power vs 3.3 V
  • 2.5 V I/O matches common logic
  • CEN enables cycle stretching
  • OE prevents bus contention
  • JTAG speeds board test/debug

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