CY7C1471BV25-133AXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1471BV25-133AXI

Datasheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C1471BV25-133AXI
CY7C1471BV25-133AXI
Datasheet


Product details

  • Architecture
    NoBL, Flow-through
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    133 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.38 V to 2.63 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial

Recommended
OPN
CY7C1471BV25-133AXI
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
CY7C1471BV25-133AXI is a 72-Mbit (2 M × 36) synchronous flow-through burst SRAM with No Bus Latency (NoBL) architecture for true back-to-back reads and writes with no wait states. It supports 133 MHz operation with 6.5 ns clock-to-data valid and registered inputs. Features include byte write, linear or interleaved 4-beat bursts, three chip enables plus OE for depth expansion, and ZZ sleep mode with data retention.

Features

  • NoBL eliminates dead bus cycles
  • Up to 133 MHz synchronous bus
  • 6.5 ns CLK-to-data valid (tCDV)
  • Data transfers every clock cycle
  • Registered synchronous inputs
  • Byte write via BWX and WE
  • Linear or interleaved burst order
  • Three chip enables (CE1-CE3)
  • Asynchronous output enable (OE)
  • Clock enable (CEN) suspends ops
  • ZZ mode automatic power-down
  • VDD 2.375–2.625 V operation

Benefits

  • Enables true back-to-back R/W
  • High throughput at 133 MHz
  • 6.5 ns access cuts latency
  • Maximizes bandwidth per clock
  • Eases timing with input regs
  • Cuts write traffic with bytes
  • Efficient cacheline burst reads
  • Simplifies depth/bank expansion
  • Quickly tri-states shared buses
  • Stall cycles without extra logic
  • Lower idle power via ZZ or CE
  • 2.5 V core eases power design

Applications

Documents

Design resources

Partner solutions

Developer community