CY7C1461KV33-133AXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1461KV33-133AXI

Datasheet
package
ea.
in stock

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CY7C1461KV33-133AXI
CY7C1461KV33-133AXI
ea.
Datasheet


Product details

  • Architecture
    NoBL, Flow-through
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    36 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    133 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    1Mb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1

Recommended
OPN
CY7C1461KV33-133AXI
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 72
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 72
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW
ea.
in stock
CY7C1461KV33-133AXI is a 36-Mbit (1M × 36) synchronous flow-through burst SRAM using NoBL™ architecture for true back-to-back read/write transfers with zero wait states at up to 133 MHz. Registered inputs and byte-write control support high-throughput buffering. It runs from 3.135 V to 3.6 V VDD with 2.5 V or 3.3 V VDDQ, and is supplied in Pb-free 100-pin TQFP over -40°C to +85°C.

Features

  • NoBL eliminates dead cycles R/W
  • Up to 133 MHz, zero wait states
  • Data transfer every clock cycle
  • Synchronous flow-through burst SRAM
  • Linear or interleaved burst order
  • 6.5 ns CLK-to-data valid (tCDV)
  • 3.135 V to 3.6 V core supply (VDD)
  • 2.375 V to 2.625 V I/O (VDDQ)
  • Byte write with BWX + WE inputs
  • 3 chip enable inputs (CE1-CE3)
  • Asynchronous OE for tri-state control
  • ZZ sleep mode preserves data

Benefits

  • Seamless write-read transitions
  • 133 MHz boosts memory bandwidth
  • 1-cycle data supports fast compute
  • Predictable sync timing simplifies bus
  • Burst modes cut controller overhead
  • 6.5 ns output speeds timing closure
  • 3.3 V core eases power integration
  • 2.5 V/3.3 V I/O fits more systems
  • Byte writes cut write traffic
  • 3 CEs enable easy bank expansion
  • OE tri-state avoids bus contention
  • Sleep cuts power with data retained

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