CY7C1381KV33-133AXIT
Active and preferred
RoHS Compliant
Lead-free

CY7C1381KV33-133AXIT

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CY7C1381KV33-133AXIT
CY7C1381KV33-133AXIT

Product details

  • Architecture
    Standard Sync, Flow-through
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 36
  • Density
    18 MBit
  • ECC
    N
  • Family
    Standard Sync
  • Frequency
    133 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    3.135 V to 3.6 V
  • Organization (X x Y)
    512Kb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1
Recommended
OPN
CY7C1381KV33-133AXIT
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 750
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 750
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1381KV33-133AXIT is an 18-Mbit (512K × 36) synchronous flow-through SRAM with common I/O and on-chip ECC. It supports 133 MHz bus operation with 6.5 ns clock-to-output and 2-1-1-1 burst reads using interleaved or linear burst counter, plus ADSC/ADSP address strobes and self-timed writes. It runs from 3.135 V to 3.6 V VDD with 2.5 V or 3.3 V VDDQ, and is available in 100-pin Pb-free TQFP for -40°C to +85°C.

Features

  • 18-Mbit sync flow-through SRAM
  • Common I/O: 512K×36 or 1M×18
  • 133 MHz bus operation
  • 6.5 ns max clock-to-data (tCDV)
  • 2-1-1-1 burst access rate
  • 2-bit wraparound burst counter
  • Linear or interleaved burst (MODE)
  • Burst start via ADSP or ADSC
  • ADV controls burst address advance
  • Byte write via BWE and BWx
  • Global write (GW) overrides bytes
  • ZZ sleep mode, 2-cycle entry/exit

Benefits

  • Fast SRAM cuts read latency
  • 18-Mbit suits cache/buffer needs
  • 133 MHz supports fast processors
  • 6.5 ns improves timing margin
  • Bursts raise throughput per clock
  • Counter reduces address logic
  • Burst mode matches CPU burst types
  • ADSP/ADSC eases CPU+cache hookup
  • ADV enables simple burst throttling
  • Byte writes cut write traffic
  • GW speeds full-word updates
  • ZZ sleep reduces idle power draw

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