CY7C1069GN30-10ZSXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1069GN30-10ZSXI

Datasheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C1069GN30-10ZSXI
CY7C1069GN30-10ZSXI
Datasheet


Product details

  • Density
    16 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 3.6 V
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Organization (X x Y)
    2M x 8
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    10 ns

Recommended
OPN
CY7C1069GN30-10ZSXI
Product Status active and preferred
Infineon Package
PG-TSOP-54
Package Name TSOP-II-54 (51-85160)
Packing Size 540
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Est. Longevity Date 2033
Launch Date 03/2022
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-54
Package Name TSOP-II-54 (51-85160)
Packing Size 540
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Est. Longevity Date 2033
Launch Date 03/2022
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
CY7C1069GN30-10ZSXI is a 16-Mbit (2M × 8) fast asynchronous CMOS SRAM with 10 ns max access time. It uses CE1/CE2, OE, and WE controls and places I/Os in high-impedance when deselected, with automatic power-down. The device operates from 2.2 V to 3.6 V over -40°C to 85°C (industrial) and supports 1.0 V data retention. Supply current is 90 mA typ, 110 mA max at fMAX. Pb-free 54-pin TSOP II.

Features

  • 16-Mbit (2M × 8) SRAM
  • 10 ns address access (tAA)
  • 10 ns read cycle time (tRC)
  • 10 ns write cycle time (tWC)
  • 5 ns OE to data valid (tDOE)
  • 2.2 V to 3.6 V VCC operation
  • 90 mA typ ICC at 100 MHz
  • Automatic power-down deselect
  • High-Z outputs when deselected
  • TTL-compatible inputs and outputs
  • 1.0 V data retention (VDR)
  • 21-bit addr (A0–A20), 8-bit I/O

Benefits

  • 10 ns access supports fast reads
  • 10 ns cycles raise data throughput
  • 5 ns OE access cuts read latency
  • 2.2–3.6 V fits 3.3 V rails
  • 90 mA typ helps power budgeting
  • Auto power-down reduces idle power
  • High-Z enables shared bus systems
  • TTL I/O eases logic interfacing
  • 1.0 V retention preserves contents
  • Retention mode lowers backup power
  • 21-bit address maps 2M locations
  • 8-bit I/O matches byte-wide MCUs

Applications

Documents

Design resources

Partner solutions

Developer community