CY7C1062GE30-10BGXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1062GE30-10BGXI

Datasheet
package
ea.
in stock

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C1062GE30-10BGXI
CY7C1062GE30-10BGXI
ea.
Datasheet

Product details

  • Density
    16 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    512K x 32
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    10 ns
Recommended
OPN
CY7C1062GE30-10BGXI
Product Status active and preferred
Infineon Package
PG-BGA-119
Package Name BGA-119 (51-85115)
Packing Size 168
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-119
Package Name BGA-119 (51-85115)
Packing Size 168
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY7C1062GE30-10BGXI is a 16-Mbit (512 K × 32) fast asynchronous CMOS SRAM with embedded ECC for single-bit error detection and correction, plus an ERR output to flag correction events. It supports 10 ns access time, runs from 2.2 V to 3.6 V over -40°C to +85°C, and is offered in a 119-ball Pb-free PBGA. Three chip enables and BA–BD byte write enables support expansion and byte-level writes.

Features

  • 16-Mbit SRAM (512K x 32)
  • Embedded ECC for single-bit fix
  • ERR output flags 1-bit ECC event
  • Address access time tAA 10 ns/15 ns
  • 4 byte enables (BA, BB, BC, BD)
  • 3 chip enables for expansion (CE1-3)
  • Automatic power-down on deselect
  • High-Z outputs when disabled
  • TTL-compatible I/O levels
  • VCC: 1.65-2.2 V or 2.2-3.6 V
  • Data retention at VDR = 1.0 V
  • ESD (HBM) > 2001 V

Benefits

  • Fits 32-bit data paths directly
  • ECC improves data integrity
  • ERR pin speeds fault handling
  • 10 ns/15 ns enables fast access
  • Byte writes cut bus bandwidth
  • 3 enables simplify bank expansion
  • Auto power-down reduces standby
  • High-Z eases bus sharing
  • TTL I/O eases logic interfacing
  • Works across common supply rails
  • 1.0 V retention saves battery
  • >2001 V ESD improves robustness

Applications

Documents

Design resources

Partner solutions

Developer community