CY7C1051H30-10ZSXIT
Active and preferred
RoHS Compliant
Lead-free

CY7C1051H30-10ZSXIT

Datasheet
package

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CY7C1051H30-10ZSXIT
CY7C1051H30-10ZSXIT
Datasheet


Product details

  • Alarms
    N
  • Density
    8 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    512K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Real Time Clock
    N
  • Speed
    10 ns
  • Watchdog Timer
    N

Recommended
OPN
CY7C1051H30-10ZSXIT
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW
CY7C1051H30-10ZSXIT is an 8-Mbit (512K × 16) fast asynchronous SRAM with embedded ECC for single-bit error correction. It operates from 2.2 V to 3.6 V over -40°C to +85°C (industrial) with 10 ns access time. Byte writes are supported via BHE/BLE, and outputs go High-Z when deselected (CE HIGH). Standby current is 20 mA typ (30 mA max) with CMOS inputs. Pb-free 44-pin TSOP II, tape-and-reel.

Features

  • 8-Mbit SRAM (512K x 16)
  • ECC with 1-bit correction
  • 10 ns address access time (tAA)
  • 2.2 V to 3.6 V VCC supply
  • 16-bit I/O with BHE/BLE byte write
  • Asynchronous CE/OE/WE controls
  • Outputs go Hi-Z on deselect
  • 90 mA typ ICC at 100 MHz
  • 20 mA typ ISB2 standby current
  • 1.0 V data retention supply (VDR)
  • 10 ns read cycle time (tRC)
  • 5 ns OE LOW to data valid (tDOE)

Benefits

  • ECC helps prevent data corruption
  • 10 ns access cuts read latency
  • 2.2–3.6 V works with 3 V rails
  • Byte writes reduce bus bandwidth
  • Async interface simplifies MCU glue
  • Hi-Z outputs enable bus sharing
  • 90 mA typ lowers active power
  • Low standby current saves energy
  • 1.0 V retention eases backup power
  • 5 ns OE access supports fast strobes
  • 10 ns cycle time boosts throughput
  • Standard pins speed hardware bring-up
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