CY7C1049GN-10VXI
Active and preferred
RoHS Compliant

CY7C1049GN-10VXI

package
ea.
in stock

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CY7C1049GN-10VXI
CY7C1049GN-10VXI
ea.

Product details

  • Density
    4 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    4.5 V to 5.5 V
  • Operating Voltage (VCCQ) range
    4.5 V to 5.5 V
  • Organization (X x Y)
    512K x 8
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    10 ns
Recommended
OPN
CY7C1049GN-10VXI
Product Status active and preferred
Infineon Package
PG-SOJ-36
Package Name SOJ-36 (51-85090)
Packing Size 570
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-SOJ-36
Package Name SOJ-36 (51-85090)
Packing Size 570
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY7C1049GN-10VXI is a 4-Mbit (512K × 8) asynchronous CMOS SRAM with 10 ns access time for fast parallel reads and writes using CE, OE, and WE control. The -10VXI option targets 4.5 V–5.5 V industrial operation (-40 to 85°C) in a Pb-free 36-pin molded SOJ package. It supports 1.0 V data retention and automatic CE power-down with 45 mA max operating current and 8 mA max standby (ISB2).

Features

  • 512K × 8-bit SRAM organization
  • tAA access time down to 10 ns
  • VCC options: 1.65–5.5 V families
  • ICC 45 mA max at 100 MHz
  • ISB2 standby 8 mA max (CMOS)
  • ISB1 standby 15 mA max (TTL)
  • OE/CE/WE control read and write
  • Three-state I/O when deselected
  • Data retention at VCC = 1.0 V
  • ICCDR 8 mA max at VCC = 1.2 V
  • tRC read cycle time 10 ns
  • tDOE OE to data 4.5 ns max

Benefits

  • Fits 8-bit MCU memory maps
  • 10 ns access supports fast buses
  • Drop-in across 1.8/3.3/5 V rails
  • Predictable power at high speed
  • Lower standby draw in idle mode
  • TTL input mode eases interfacing
  • Simple async interface, no clock
  • High-Z I/O enables shared bus
  • Keeps data with backup supply
  • Low retention current saves energy
  • Short read cycle cuts latency
  • Fast OE improves bus turnarounds
Documents

Design resources

Partner solutions

Developer community

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