CY62167G30-45BVXI
Active and preferred
RoHS Compliant
Lead-free

CY62167G30-45BVXI

Datasheet
package
ea.
in stock

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CY62167G30-45BVXI
CY62167G30-45BVXI
ea.
Datasheet


Product details

  • Density
    16 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    1M x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial

Recommended
OPN
CY62167G30-45BVXI
Product Status active and preferred
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 4800
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 4800
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
TW
ea.
in stock
CY62167G30-45BVXI is a 16-Mbit (1M × 16 or 2M × 8) CMOS static RAM with embedded ECC for single-bit error correction. It operates from 2.2 V to 3.6 V over -40°C to 85°C with 45 ns access time and TTL-compatible I/O. VCC operating current is 35 mA max at 22.22 MHz. Automatic and byte power-down reduce standby current to 1.5 µA typical and 8 µA max. It is supplied in a Pb-free 48-ball VFBGA.

Features

  • 16-Mbit SRAM; 1M×16 or 2M×8
  • Embedded ECC single-bit correction
  • ERR output flags corrected errors
  • VCC operating 2.2 V to 3.6 V
  • 45 ns read cycle time (tRC)
  • 45 ns write cycle time (tWC)
  • Auto power-down standby 1.5 µA typ
  • 8 µA max standby current (ISB1)
  • 1.0 V data retention (VDR)
  • TTL-compatible inputs and outputs
  • Byte write via BHE/BLE enables
  • 10 pF max input/output capacitance

Benefits

  • Flexible bus width cuts redesign
  • ECC corrects 1-bit memory errors
  • ERR pin enables fast fault logging
  • 2.2–3.6 V fits 3.3 V systems
  • 45 ns access supports fast CPUs
  • 45 ns writes reduce wait states
  • 1.5 µA typ extends battery life
  • 8 µA max lowers standby budget
  • 1.0 V retention preserves data
  • TTL I/O eases legacy interfacing
  • Byte enables reduce write power
  • Low C eases signal integrity
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