CY62167ELL-45ZXI
Active and preferred
RoHS Compliant
Lead-free

CY62167ELL-45ZXI

Datasheet
package
ea.
in stock

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CY62167ELL-45ZXI
CY62167ELL-45ZXI
ea.
Datasheet


Product details

  • Density
    16 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    4.5 V to 5.5 V
  • Organization (X x Y)
    1M x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial

Recommended
OPN
CY62167ELL-45ZXI
Product Status active and preferred
Infineon Package
PG-TSOP-48
Package Name TSOP-I-48 (51-85183)
Packing Size 480
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
CN,US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-48
Package Name TSOP-I-48 (51-85183)
Packing Size 480
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
CN,US
ea.
in stock
CY62167ELL-45ZXI is a 16-Mbit CMOS SRAM organized as 1 M × 16 (or 2 M × 8) for 5 V processors with TTL input levels. It operates from 4.5 V to 5.5 V over -40°C to 85°C and is specified for 45 ns access. Low-power design supports automatic power-down standby at 1.5 µA typ (12 µA max) and active current 2.2 mA typ at 1 MHz (4.0 mA max). It is offered in a 48-pin TSOP I, Pb-free package.

Features

  • 16-Mbit SRAM, 1 M×16 or 2 M×8
  • 45 ns read/write cycle time
  • 4.5 V to 5.5 V VCC operation
  • 2.2 mA typ at 1 MHz active
  • 1.5 µA typ standby power-down
  • 12 µA max standby current
  • TTL input levels supported
  • CE1/CE2/OE chip control inputs
  • BLE/BHE byte write enables
  • High-Z outputs on disable
  • >2001 V ESD (MIL-STD-883)
  • Latch-up current >200 mA

Benefits

  • Flexible 16-bit or 8-bit bus design
  • 45 ns access boosts CPU throughput
  • 5 V supply fits legacy designs
  • Low active current cuts power draw
  • µA standby extends battery life
  • Low max standby eases power budget
  • Direct TTL interfacing reduces glue
  • CE/OE simplify memory expansion
  • Byte writes reduce write bandwidth
  • High-Z avoids bus contention
  • High ESD cuts handling failures
  • Latch-up immunity improves uptime

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