CY62157H30-45BVXAT
Active and preferred
RoHS Compliant
Lead-free

CY62157H30-45BVXAT

Datasheet
package

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CY62157H30-45BVXAT
CY62157H30-45BVXAT
Datasheet


Product details

  • Density
    16 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    512K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Automotive(A)
  • Speed
    45 ns

Recommended
OPN
CY62157H30-45BVXAT
Product Status active and preferred
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
CY62157H30-45BVXAT is an 8-Mbit (512K × 16) CMOS MoBL SRAM with embedded ECC for single-bit error detect and correct. It supports 45 ns access at 2.2 V to 3.6 V over -40°C to 85°C, with TTL-compatible I/Os. Operating ICC is 36 mA max at fMAX (9 mA max at 1 MHz). Standby is 16 µA max (5.5 µA typ) with dual chip enable and byte power-down via BHE/BLE. Pb-free 48-ball VFBGA (BV) package.

Features

  • 8-Mbit (512K x 16) SRAM
  • Embedded ECC single-bit correction
  • 16-bit I/O with byte enables
  • 45 ns read/write cycle time
  • 2.2 V to 3.6 V VCC supply
  • 1.0 V data retention (VDR)
  • 5.5 µA typ standby (ISB)
  • 36 mA max ICC at fMAX
  • >2001 V ESD (MIL-STD-883)
  • OE/WE/CE tri-state output control

Benefits

  • ECC helps protect data integrity
  • Byte writes cut bus activity
  • 45 ns access supports fast CPUs
  • 2.2–3.6 V fits common 3 V rails
  • 1.0 V retention lowers backup power
  • 5.5 µA standby extends battery life
  • Tri-state outputs ease bus sharing
  • Dual chip enables simplify decoding
  • High ESD improves handling yield
  • CMOS SRAM enables instant reads

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