CY62157H30-45BVXA
Active and preferred
RoHS Compliant
Lead-free

CY62157H30-45BVXA

Datasheet
package

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CY62157H30-45BVXA
CY62157H30-45BVXA
Datasheet


Product details

  • Density
    8 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    512K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Automotive(A)
  • Speed
    45 ns

Recommended
OPN
CY62157H30-45BVXA
Product Status active and preferred
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 960
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Est. Longevity Date 2033
Launch Date 03/2022
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 960
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Est. Longevity Date 2033
Launch Date 03/2022
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
CY62157H30-45BVXA is an AEC-Q100 qualified 8-Mbit (512K × 16) CMOS SRAM with embedded ECC for single-bit error correction. It operates from 2.2 V to 3.6 V over −40°C to +85°C, with 45 ns access time. Dual chip-enable and byte write (BHE/BLE) support flexible memory mapping, while automatic power-down enables 5.5 μA typical (16 μA max) standby and 29 mA typical operating current at fMAX.

Features

  • 8-Mbit SRAM (512K x 16)
  • Embedded ECC single-bit correction
  • 45 ns read/write cycle time
  • VCC operating 2.2 V to 3.6 V
  • Standby current 5.5 µA typ
  • Standby current 16 µA max
  • Operating ICC 36 mA max at fMAX
  • 1.0 V data retention mode
  • Byte write enables (BHE, BLE)
  • Dual chip-enable inputs CE1/CE2
  • OE to High-Z in 18 ns max
  • TTL-compatible I/O levels

Benefits

  • ECC improves data integrity
  • 45 ns supports fast CPU access
  • 2.2-3.6 V fits 3.3 V rails
  • µA standby extends battery life
  • Low max standby cuts idle power
  • 36 mA max eases power budgeting
  • 1.0 V retention saves backup power
  • Byte enables cut write energy
  • Dual CE supports bank selection
  • Fast HI-Z eases bus sharing
  • TTL I/O simplifies interfacing
  • 20 mA sink drives loads directly

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