CY62146ELL-45ZSXI
Active and preferred
RoHS Compliant

CY62146ELL-45ZSXI

Data Sheet
package
ea.
in stock

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY62146ELL-45ZSXI
CY62146ELL-45ZSXI
ea.
Data Sheet

Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    4.5 V to 5.5 V
  • Operating Voltage (VCCQ) max
    5.5 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    45 ns
Recommended
OPN
CY62146ELL-45ZSXI
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 675
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 675
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY62146ELL-45ZSXI is a 4-Mbit (256K × 16) CMOS static RAM for 5 V systems, specified for 45 ns access. It operates from 4.5 V to 5.5 V over -40°C to +85°C (industrial range) and supports TTL input levels. Automatic CE power-down reduces standby to 2.5 µA typical (7 µA max). Active current is 3.5 mA typical at 1 MHz, with ICC up to 20 mA at fmax. Supplied in a 44-pin Pb-free TSOP II.

Features

  • 256K × 16 CMOS static RAM
  • 45 ns read/write cycle time
  • 4.5 V to 5.5 V VCC operation
  • 3.5 mA typ ICC at 1 MHz
  • 2.5 µA typ standby (CE HIGH)
  • 7 µA max standby current
  • Automatic CE power-down (ISB2)
  • Data retention at VCC = 2 V
  • ICCDR max 8.8 µA at 2 V
  • Byte write via BHE/BLE
  • TTL-compatible input levels
  • Tri-state outputs via OE/CE

Benefits

  • Fast 45 ns boosts CPU access
  • 5 V rail fits legacy designs
  • Low 3.5 mA cuts active power
  • 2.5 µA standby extends battery
  • Auto power-down saves energy
  • 2 V retention preserves data
  • 8.8 µA max lowers backup drain
  • Byte enables reduce write power
  • OE/CE tri-state eases bus sharing
  • TTL inputs simplify interfacing
  • High-Z prevents bus contention
  • SRAM avoids refresh complexity

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }