CY62128ELL-45SXA
Active and preferred
RoHS Compliant

CY62128ELL-45SXA

Data Sheet
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CY62128ELL-45SXA
CY62128ELL-45SXA
Data Sheet

Product details

  • Density
    1 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    5.5 V
  • Operating Voltage range
    4.5 V to 5.5 V
  • Organization (X x Y)
    128K x 8
  • Peak Reflow Temp
    260 °C
  • Qualification
    Automotive
  • Speed
    45 ns
Recommended
OPN
CY62128ELL-45SXA
Product Status active and preferred
Infineon Package
PG-DSO-32
Package Name SOIC-32 (51-85081)
Packing Size 500
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-DSO-32
Package Name SOIC-32 (51-85081)
Packing Size 500
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY62128ELL-45SXA is a 1-Mbit (128K × 8) CMOS SRAM for 4.5 V to 5.5 V systems with 45 ns access. Automotive-A grade supports -40°C to +85°C operation. Low-power design includes automatic CE power-down with 1 µA typical standby (4 µA max) and 1.3 mA typical active current at 1 MHz. It targets portable and automotive embedded memory, uses TTL input levels, and comes in a Pb-free 32-pin 450-mil SOIC.

Features

  • 128K × 8 SRAM organization
  • 45 ns read cycle time (tRC)
  • 4.5 V to 5.5 V VCC operation
  • 1.3 mA typ ICC at 1 MHz
  • 1 µA typ standby current
  • Auto CE power-down (ISB2)
  • CE1/CE2 and OE chip controls
  • High-Z outputs when deselected
  • TTL-compatible input levels
  • VIH 2.2 V, VIL 0.8 V thresholds
  • 10 pF max input capacitance
  • tDOE 22 ns OE to data valid

Benefits

  • Fast 45 ns cycles cut latency
  • 5 V supply fits legacy designs
  • 1.3 mA typ lowers active power
  • 1 µA standby extends battery life
  • Auto power-down saves idle energy
  • CE1/CE2 simplify memory expansion
  • High-Z outputs ease bus sharing
  • TTL levels ease MCU/CPU interface
  • Defined thresholds reduce errors
  • Low capacitance eases timing margins
  • 22 ns OE read improves response
  • Lower standby cuts thermal load

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Documents

Design resources

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Developer community

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