CY25100SXCF
not for new design
RoHS Compliant
Lead-free

CY25100SXCF

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CY25100SXCF
CY25100SXCF


Product details

  • Core/IO Operating Voltages ((V))
    3.3
  • Features
    Field Programmable Spread Spectrum Clock Generator
  • I/O Voltage ((V))
    3.3
  • Input Frequency range
    8 MHz to 166 MHz
  • Input Type
    Xtal/Ref-in CMOS
  • Lead Ball Finish
    Pure Sn
  • On-chip Clock Generation (PLL)
    1
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3.13 V to 3.45 V
  • Output Frequency range
    3 MHz to 200 MHz
  • Output Signal Type
    CMOS
  • Outputs
    2
  • Peak Reflow Temp
    260 °C
  • Publish in NPSG
    N
  • Publish in PSG
    Y
  • Qualification
    Commercial
  • Spread Spectrum
    Y

OPN
CY25100SXCF
Product Status not for new design
Infineon Package
Package Name SOIC-8 (51-85066 )
Packing Size 485
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
CN

Product Status not for new design
Infineon Package
Package Name SOIC-8 (51-85066 )
Packing Size 485
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
CN
The CY25100SXCF is a programmable spread spectrum clock generator for EMI reduction in high-speed digital systems. It supports 8 to 166 MHz input and generates two CMOS outputs from 3 to 200 MHz. Operating at 3.13 to 3.45 V and 0 to 70°C, it features an on-chip PLL, programmable spread spectrum (center ±0.25% to ±2.5%, down –0.5% to –5.0%), 3.3 V I/O, and RoHS compliance. Typical uses include EMI reduction in consumer and industrial electronics.

Features

  • Field and factory programmable
  • Output frequency: 3 to 200 MHz
  • Programmable spread: ±0.25% to ±2.5%
  • Down spread: –0.5% to –5.0%
  • Integrated PLL and SSC technology
  • Crystal load capacitor: 12 to 60 pF
  • Low cycle-to-cycle jitter
  • Two clock outputs: SSCLK, REFCLK
  • Spread spectrum on/off control
  • Power down or output enable
  • Output duty: 45–55% (SSCLK)
  • Slew rate up to 4.0 V/ns

Benefits

  • Enables fast EMI-compliant clock design
  • Flexible for late design changes
  • Reduces EMI for easier compliance
  • Eliminates external load capacitors
  • Reliable clock with low jitter
  • Two outputs support multiple domains
  • Programmable for various applications
  • Quick power cycling saves energy
  • Spread control adapts to system needs
  • Consistent output duty for integrity
  • High slew rate supports fast edges
  • Field programmability reduces inventory

Applications

Documents

Design resources

Developer community