Please note that this is an end of life product. See newer alternative product version Please note that this is an end of life product. See newer alternative product version
CY23S05SXC-1H
END OF LIFE
discontinued
RoHS Compliant
Lead-free

CY23S05SXC-1H

END OF LIFE
Datasheet
package

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CY23S05SXC-1H
CY23S05SXC-1H
Datasheet


Product details

  • Category
    Zero Delay Buffers
  • Core/IO Operating Voltages ((V))
    3.3
  • Features
    Low Cost 3.3V Spread Aware Zero Delay Buffer
  • Function
    See datasheet
  • I/O Voltage ((V))
    3.3
  • Input Frequency range
    10 MHz to 133 MHz
  • Input Type
    LVCMOS/LVTTL
  • Lead Ball Finish
    Pure Sn
  • On-chip Clock Generation (PLL)
    1
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3 V to 3.6 V
  • Output Frequency range
    10 MHz to 133 MHz
  • Output Signal Type
    LVCMOS
  • Outputs
    5
  • Peak Reflow Temp
    260 °C
  • Publish in NPSG
    N
  • Publish in PSG
    Y
  • Qualification
    Commercial
  • Spread Spectrum
    Y

OPN
CY23S05SXC-1H
Product Status discontinued
Infineon Package
PG-DSO-8
Package Name SOIC-8 (51-85066 )
Packing Size 1940
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW

Product Status discontinued
Infineon Package
PG-DSO-8
Package Name SOIC-8 (51-85066 )
Packing Size 1940
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW
The CY23S05SXC-1 H is a low-cost, 3.3 V spread spectrum aware zero delay buffer with five LVCMOS outputs for clock distribution in commercial systems. It supports 10 to 133 MHz input/output, features on-chip PLL for zero input-output delay, less than 250 ps output skew, and 200 ps cycle-to-cycle jitter. Operating from 3.0 to 3.6 V and 0 to 70°C, it is halogen free, RoHS compliant, and supplied in an 8-pin SOIC package.

Features

  • On-chip PLL locks to input clock
  • Zero input-output propagation delay
  • Output-output skew less than 250 ps
  • Device-device skew less than 700 ps
  • Cycle-to-cycle jitter less than 200 ps
  • Test mode to bypass PLL (CY23S09)
  • Spread Aware, passes Spread Spectrum
  • 3.3 V operation, 0.65 μm CMOS tech
  • Input reference 5 V tolerant
  • One input drives multiple outputs
  • Output frequency up to 133 MHz
  • Duty cycle 40% to 60%

Benefits

  • Ensures precise clock synchronization
  • Reduces timing errors across outputs
  • Reliable multi-device clock distribution
  • Minimizes system jitter for signal
  • Supports EMI reduction techniques
  • Flexible test/debug with PLL bypass
  • Compatible with modern 3.3 V systems
  • Handles 5 V input for legacy support
  • High output count simplifies design
  • Wide frequency range for many uses
  • Stable duty cycle for timing accuracy
  • Robust CMOS for low power, high speed

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Design resources

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