OptiMOS™ and StrongIRFET™ power MOSFETs in PQFN 3.3 x 3.3 package

OptiMOS™ and StrongIRFET™ low-voltage power MOSFET in a PQFN 3.3 x 3.3 package

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Overview

The Power Quad Flat No-lead (PQFN) 3.3 x 3.3 mm MOSFET package offers high efficiency and compact size.

Key Features

  • Low RDS(on)
  • Small outline package
  • Low gate charge
  • Super logic level (2.5 V) available
  • Logic level (4.5 V) available

Products

About

Efficient and space-saving solutions for a wide range of applications

This family of small-outline package MOSFETs is ideal for applications requiring enhanced efficiency and power density. The PQFN MOSFET offering is available with StrongIRFET™ and OptiMOS™ MOSFET technologies, offering customers optimized solutions for both general-purpose and high-performance applications.

Low-voltage power MOSFET portfolio in PQFN 3.3x3.3 mm package

The portfolio is composed of single N-channel and P-channel MOSFETs as well as dual-channel MOSFETs. The family offers a wide range of voltages to select from various design requirements, from -150 V to 250 V.

Standard Drain-Down and Source-Down pin configurations are available within PQFN 3.3x3.3 package offerings as well as two footprint options:

  • Corner-Gate: Easy adoption into existing PCB designs
  • Center-Gate: Optimized for paralleling

The PQFN 3.3x3.3 Source-Down Dual Side Cooling package features active trenches on the source side of the silicon die generate heat, which is dissipated directly into the PCB through a thermal pad. This improves the RthJC of the product family by over 20%, from 1.8 K/W to 1.4 K/W.

Additionally, the exposed top side improves RthJC, top from 20 K/W (for over-molded) down to 0.7 K/W. A heatsink on top of the device can take advantage of this low RthJC, top, enabling up to three times more power dissipation compared to an over-molded package.

Select the package best-suited for your needs from the broadest portfolio of MOSFETs.

Key benefits of PQFN 3.3x3.3 MOSFETs

The family of PQFN 3.3x3.3 offers flexibility in gate drive with 4.5 V and 2.5 V gate drive capability. The low RDS(on) enables high efficiency in overall system design. The small outline package results in board space reduction, while the low gate charge reduces the switching and drive losses, thereby improving design efficiency.

Efficient and space-saving solutions for a wide range of applications

This family of small-outline package MOSFETs is ideal for applications requiring enhanced efficiency and power density. The PQFN MOSFET offering is available with StrongIRFET™ and OptiMOS™ MOSFET technologies, offering customers optimized solutions for both general-purpose and high-performance applications.

Low-voltage power MOSFET portfolio in PQFN 3.3x3.3 mm package

The portfolio is composed of single N-channel and P-channel MOSFETs as well as dual-channel MOSFETs. The family offers a wide range of voltages to select from various design requirements, from -150 V to 250 V.

Standard Drain-Down and Source-Down pin configurations are available within PQFN 3.3x3.3 package offerings as well as two footprint options:

  • Corner-Gate: Easy adoption into existing PCB designs
  • Center-Gate: Optimized for paralleling

The PQFN 3.3x3.3 Source-Down Dual Side Cooling package features active trenches on the source side of the silicon die generate heat, which is dissipated directly into the PCB through a thermal pad. This improves the RthJC of the product family by over 20%, from 1.8 K/W to 1.4 K/W.

Additionally, the exposed top side improves RthJC, top from 20 K/W (for over-molded) down to 0.7 K/W. A heatsink on top of the device can take advantage of this low RthJC, top, enabling up to three times more power dissipation compared to an over-molded package.

Select the package best-suited for your needs from the broadest portfolio of MOSFETs.

Key benefits of PQFN 3.3x3.3 MOSFETs

The family of PQFN 3.3x3.3 offers flexibility in gate drive with 4.5 V and 2.5 V gate drive capability. The low RDS(on) enables high efficiency in overall system design. The small outline package results in board space reduction, while the low gate charge reduces the switching and drive losses, thereby improving design efficiency.

Documents

Documents

Design resources

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