S28HL512TFPBHV013
Active and preferred
RoHS Compliant
Lead-free

S28HL512TFPBHV013

package

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S28HL512TFPBHV013
S28HL512TFPBHV013

Product details

  • Density
    512 MBit
  • Family
    HS-T
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    166 / 166
  • Interfaces
    Octal
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2037
  • Qualification
    Industrial
Recommended
OPN
S28HL512TFPBHV013
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
S28HL512TFPBHV013 is a 512 Mbit SEMPER™ NOR flash in the HS‑T family with an octal interface for code and data storage in embedded systems. It runs from 2.7 V to 3.6 V over -40°C to 105°C and supports 166 MHz SDR/DDR operation with up to 333 MByte/s interface bandwidth. Built-in ECC, interface/data CRC, Endurance Flex wear leveling, SafeBoot, and AutoBoot help improve integrity and startup robustness.

Features

  • 45-nm MIRRORBIT™ stores 2 bits/cell
  • Uniform or hybrid sector architecture
  • 256 or 512-byte program buffer
  • 1024-byte OTP secure silicon array
  • Octal 8S-8S-8S and 8D-8D-8D
  • JEDEC JESD251 xSPI compliant
  • Data strobe (DS) for read capture
  • ECC on 16-byte units, SECDED
  • SafeBoot status detects init faults
  • AutoBoot outputs data after reset
  • LBP and ASP sector protection
  • Hardware or software reset support

Benefits

  • Higher density with fewer cells
  • Fits boot code and data layouts
  • Faster page program transactions
  • Stores IDs and secrets securely
  • High throughput on few signal pins
  • Easier host support via xSPI
  • Improves timing margin at high speed
  • Reduces bit errors in stored code
  • Enables recovery after bad power-up
  • Cuts boot time and host firmware steps
  • Prevents unauthorized code changes
  • Simplifies robust system reset design
Documents

Design resources

Partner solutions

Developer community

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