Active and preferred
RoHS Compliant
Lead-free

S26HS02GTFPBHB053

Data Sheet
package

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S26HS02GTFPBHB053
S26HS02GTFPBHB053
Data Sheet

Product details

  • Classification
    ISO 26262-compliant
  • Density
    2 GBit
  • Family
    HS-T
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 166
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature
    -40 °C to 105 °C
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2037
  • Publish in NPSG
    N
  • Publish in PSG
    N
  • Qualification
    Automotive
Recommended
OPN
S26HS02GTFPBHB053
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-24801)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-24801)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S26HS02GTFPBHB053 is a 2 Gb SEMPER™ NOR Flash memory built on Infineon's 45-nm MIRRORBIT™ technology, supporting HYPERBUS™ and legacy SPI interfaces with JEDEC JESD251 compliance. It achieves up to 332 MBps DDR read speeds at 166 MHz, features configurable sector architecture, and robust safety including ISO 26262 ASIL-B compliance and ECC. Operating at 1.7–2.0 V, it offers 2,560,000 cycles endurance and 25-year retention for automotive and industrial use.

Features

  • MIRRORBIT technology stores 2 bits/cell
  • HYPERBUS interface supports DDR up to 332
  • JEDEC JESD251 xSPI compliant
  • Legacy SPI interface (SDR up to 21 MBps)
  • Flexible sector architecture: uniform
  • Page programming buffer: 256 or 512 bytes
  • OTP secure silicon region: 1024 bytes
  • Functional safety: ISO26262 ASIL B compliant
  • Interface and data integrity CRC
  • Built-in ECC: SECDED on memory array data
  • Advanced sector protection
  • Hardware reset via CS# or RESET# pin

Benefits

  • 2 bits/cell increases memory density
  • 332 MBps DDR enables fast data access
  • xSPI compliance ensures broad compatibility
  • Dual interface eases system integration
  • Flexible sectors suit varied application
  • Large buffer boosts programming speed
  • OTP region secures sensitive data
  • Functional safety supports automotive use
  • CRC/ECC enhance data reliability
  • Sector protection prevents accidental
  • Hardware reset improves system robustness

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }