Active and preferred
RoHS Compliant
Lead-free

S25FS256SDSNFI000

Data Sheet
package
board
software
ea.
in stock

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

S25FS256SDSNFI000
S25FS256SDSNFI000
ea.
Data Sheet

Product details

  • Density
    256 MBit
  • Family
    FS-S
  • Interface Bandwidth
    80 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    133 / 80
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Matte Tin Plating
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Industrial
Recommended
OPN
S25FS256SDSNFI000
Product Status active and preferred
Infineon Package
PG-WSON-8
Package Name DFN-8 (002-15552)
Packing Size 676
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-WSON-8
Package Name DFN-8 (002-15552)
Packing Size 676
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The S25FS256SDSNFI000 is a 256 Mbit (32 MB) SPI NOR Flash based on 65-nm MIRRORBIT™ technology, supporting single, dual, and quad I/O plus DDR read up to 80 MBps. It operates from 1.7 V to 2.0 V and is qualified for automotive AEC-Q100 Grade 1 (-40°C to +125°C) and industrial grades. Features include a 256/512-byte program buffer, flexible sector options, 100,000 program/erase cycles, and 20-year data retention. Ideal for code storage, XIP, and embedded applications.

Features

  • Serial peripheral interface (SPI)
  • Double data rate (DDR) option
  • 24- or 32-bit address options
  • Multi I/O command support
  • Normal, Fast, Dual, Quad, DDR Quad I/O reads
  • Burst Wrap, Continuous (XIP), QPI modes
  • 256- or 512-byte page programming buffer
  • Automatic ECC, single-bit error correction
  • Hybrid and uniform sector erase options
  • 100,000 program-erase cycles minimum
  • 20 year data retention minimum
  • 1.7 V to 2.0 V supply voltage

Benefits

  • Flexible SPI supports many host controllers
  • DDR and Quad I/O enable high data rates
  • 32-bit addressing supports large designs
  • Multi I/O boosts read/write performance
  • Multiple read modes fit varied applications
  • XIP/QPI enable execute-in-place operation
  • Large page buffer speeds up programming
  • ECC improves data reliability
  • Flexible erase options ease partitioning
  • High endurance for long device lifetime
  • Long retention secures critical data
  • Low voltage reduces power consumption

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }