Active and preferred
RoHS Compliant

IQE006NE2LM5

OptiMOS™ 25 V low-voltage power MOSFET in PQFN 3.3x3.3 Source-Down package with industry leading RDS(on).
Data Sheet
package
board
ea.
in stock

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IQE006NE2LM5
IQE006NE2LM5
ea.
Data Sheet

Product details

  • Budgetary Price €/1k
    0.66
  • Ciss
    4100 pF
  • Coss
    1700 pF
  • ID (@25°C) max
    298 A
  • IDpuls max
    1192 A
  • Operating Temperature
    -55 °C to 150 °C
  • Package
    PQFN 3.3x3.3 Source-Down
  • Polarity
    N
  • Ptot max
    89 W
  • QG (typ @4.5V)
    28.5 nC
  • QG (typ @10V)
    61.7 nC
  • RDS (on) (@10V) max
    0.65 mΩ
  • RDS (on) (@4.5V) max
    0.8 mΩ
  • RthJA max
    60 K/W
  • RthJC max
    1.4 K/W
  • Rth
    1.4 K/W
  • VDS max
    25 V
  • VGS(th)
    1.3 V to 2 V
  • VGS max
    16 V
Recommended
OPN
IQE006NE2LM5ATMA1
Product Status active and preferred
Infineon Package
PG-TSON-8
Package Name PQFN 3.3x3.3 Source-Down
Packing Size 5000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSON-8
Package Name PQFN 3.3x3.3 Source-Down
Packing Size 5000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The innovative Source-Down OptiMOS™ low-voltage power MOSFET 25 V comes in a PQFN3.3x3.3 package size, making it easy to use in the same PCB routing as the Drain-Down solution. In the same package outline of 3.3x3.3mm, the new Source-Down shows an industry benchmark RDS(on) by reducing the current standard RDS(on) of about 30 percent and shows a significant shrink of form factor.

Features

  • RDS(on) reduction up to 30%
  • Superior thermal management option
  • Optimized layout possibilities
  • Two footprint versions available

Benefits

  • Higher current capability
  • Highest power density and performance
  • Shrink of form factor
  • SuperSO8 performance in smaller package
  • Optimized PCB parasitics
  • Decrease of RthJA and RthJC
  • Better transfer of power losses
  • Double-side cooling
  • Source-Down for existing PCB
  • Center-Gate optimizes parallelization

Documents

Documents

Design resources

Partner solutions

Developer community

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