CY7C2670KV18-450BZI
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CY7C2670KV18-450BZI

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CY7C2670KV18-450BZI
CY7C2670KV18-450BZI

Product details

  • Architecture
    DDR-II+ CIO, ODT
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 36
  • Density
    144 MBit
  • ECC
    N
  • Family
    DDR-II+ CIO, ODT
  • Frequency
    450 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • On-Die Termination
    Y
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    2.5
Recommended
OPN
CY7C2670KV18-450BZI
Product Status active and preferred
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 105
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant No
Infineon stock last updated:

Product Status
Active
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 105
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C2670KV18-450BZI is a 144-Mbit (4 M × 36) DDR II+ synchronous pipelined SRAM with two-word burst architecture and 2.5-cycle read latency. It runs up to 450 MHz clock with double data rate transfers (up to 900 MT/s) and includes echo clocks (CQ/CQ) plus QVLD for data capture. Core VDD is 1.7 V to 1.9 V and VDDQ is 1.4 V to VDD. It comes in a 165-ball FBGA package for industrial range.

Features

  • 144-Mbit (4 M × 36) DDR II+ SRAM
  • 550 MHz clock, 1100 MHz data rate
  • Two-word burst architecture
  • 2.5-cycle read latency (DOFF high)
  • DDR I mode, 1-cycle latency (DOFF low)
  • Two input clocks K/K (DDR timing)
  • Echo clocks CQ/CQ for data capture
  • QVLD pin flags valid read data
  • On-die termination for D,BWS,K/K
  • ZQ pin sets output impedance (RQ)
  • Byte write via BWS[3:0]
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • High bandwidth at 550 MHz clocking
  • Burst reduces address bus toggling
  • Select latency to fit timing margin
  • Precise DDR timing with K/K clocks
  • CQ/CQ simplifies receiver capture
  • QVLD cuts read timing uncertainty
  • ODT removes external term resistors
  • Fewer parts lowers BOM and area
  • ZQ tracking improves signal integrity
  • Byte writes ease RMW and save cycles
  • Posted-write avoids read/write clash
  • JTAG speeds board test and debug

Applications

Documents

Design resources

Partner solutions

Developer community

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