CY7C1480V33-167AXC
Active and preferred
RoHS Compliant
Lead-free

CY7C1480V33-167AXC

Datasheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C1480V33-167AXC
CY7C1480V33-167AXC
Datasheet


Product details

  • Architecture
    Standard Sync, Pipeline SCD
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    Standard Sync
  • Frequency
    167 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
  • Read Latency (Cycles)
    1

Recommended
OPN
CY7C1480V33-167AXC
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
CY7C1480V33-167AXC is a 72-Mbit (2M × 36) pipelined synchronous SRAM for high-speed cache and buffer memory. It runs from a 3.3 V core with 2.5 V/3.3 V JEDEC JESD8-5 I/O, and supports bus operation up to 167 MHz with 3.4 ns clock-to-output delay. Registered I/O, a 2-bit linear/interleaved burst counter, byte and global write, JTAG boundary scan, and ZZ sleep mode are included for power-down standby.

Features

  • Bus operation up to 200 MHz
  • 72-Mbit (2M × 36) sync SRAM
  • Registered I/O for pipelining
  • Clock-to-output tCO max 3.0 ns
  • Supports 3-1-1-1 burst access
  • Linear or interleaved burst mode
  • 2-bit wraparound burst counter
  • ADSP/ADSC address strobe inputs
  • Byte writes via BWE and BWX
  • Global write (GW) writes all bytes
  • ZZ sleep mode, IDDZZ max 120 mA
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • 200 MHz supports high throughput
  • 36-bit width fits datapath buses
  • Pipelining boosts system frequency
  • 3.0 ns tCO helps timing closure
  • 3-1-1-1 bursts cut read latency
  • Match Intel or linear burst CPUs
  • Internal counter reduces logic
  • Flexible strobes ease interfacing
  • Byte write updates only needed data
  • Global write speeds block fills
  • Sleep mode lowers standby power
  • JTAG scan speeds board debug

Applications

Documents

Design resources

Partner solutions

Developer community