CY7C1472V33-200AXC
Active and preferred
RoHS Compliant
Lead-free

CY7C1472V33-200AXC

Datasheet
package

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CY7C1472V33-200AXC
CY7C1472V33-200AXC
Datasheet


Product details

  • Architecture
    NoBL, Pipeline
  • Bank Switching
    N
  • Data Width
    x 18
  • Density
    72 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    200 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    4Mb x 18
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
  • Read Latency (Cycles)
    1

Recommended
OPN
CY7C1472V33-200AXC
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
CY7C1472V33-200AXC is a 72-Mbit synchronous pipelined burst SRAM organized as 4M × 18 with No Bus Latency (NoBL) for zero-wait-state read/write transitions. It supports 200 MHz operation with 3.0 ns clock-to-output, fully registered inputs/outputs, and an on-chip burst counter for up to four linear or interleaved accesses per address. Byte write uses BWa/BWb. It runs from a 3.3 V core with 2.5 V/3.3 V I/O and comes in a Pb-free 100-pin TQFP.

Features

  • 72-Mbit sync pipelined burst SRAM
  • NoBL logic for zero bus latency
  • 200 MHz bus ops, zero wait states
  • Fully registered inputs and outputs
  • 3.0 ns clock-to-output (tCO)
  • On-chip burst counter, 4-beat burst
  • Linear or interleaved burst order
  • Byte write via BW[x] byte selects
  • Single 3.3 V VDD supply (3.135-3.6 V)
  • 3.3 V or 2.5 V VDDQ I/O supply
  • ZZ sleep mode; 2tCYC entry/exit
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • Zero-latency boosts throughput
  • 200 MHz supports fast datapaths
  • Registered I/O eases timing closure
  • 3.0 ns tCO cuts read data latency
  • 4-beat bursts reduce addr overhead
  • Selectable burst supports controllers
  • Byte writes speed RMW operations
  • Single 3.3 V core simplifies power
  • 2.5/3.3 V I/O fits mixed-voltage
  • ZZ mode cuts standby power (120 mA)
  • 2tCYC wake-up enables fast resume
  • JTAG scan simplifies board test

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