CY7C1380KV33-167AXC
Active and preferred
RoHS Compliant
Lead-free

CY7C1380KV33-167AXC

Datasheet
package
ea.
in stock

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CY7C1380KV33-167AXC
CY7C1380KV33-167AXC
ea.
Datasheet


Product details

  • Architecture
    Standard Sync, Pipeline SCD
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 36
  • Density
    18 MBit
  • ECC
    N
  • Family
    Standard Sync
  • Frequency
    167 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3.135 V to 3.6 V
  • Organization (X x Y)
    512Kb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Commercial
  • Read Latency (Cycles)
    2

Recommended
OPN
CY7C1380KV33-167AXC
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 360
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Est. Longevity Date 2031
Launch Date 03/2022
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 360
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Est. Longevity Date 2031
Launch Date 03/2022
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
ea.
in stock
CY7C1380KV33-167AXC is an 18-Mbit synchronous pipelined SRAM organized as 512K × 36 with a 2-bit internal burst counter. It supports registered inputs/outputs for 3-1-1-1 burst accesses at up to 167 MHz (3.4 ns access). The device uses 3.135 V to 3.6 V VDD and 2.375 V to 3.6 V VDDQ I/O, includes ZZ sleep and IEEE 1149.1 JTAG boundary scan, and is offered in a Pb-free 100-pin TQFP (commercial).

Features

  • Bus operation up to 250 MHz
  • 2.5 ns clock-to-output (tCO)
  • Registered I/O for pipelining
  • 3-1-1-1 burst access
  • Linear or interleaved burst order
  • 2-bit on-chip burst counter
  • Byte write via BWE and BWX
  • Global write (GW) all bytes
  • Common I/O; async OE tri-state
  • ZZ sleep mode with data retention
  • Core VDD 3.135 V to 3.6 V
  • I/O VDDQ 2.375–2.625 V or 3.3 V

Benefits

  • 250 MHz supports fast SRAM buses
  • 2.5 ns tCO cuts read latency
  • Pipelining improves throughput
  • 3-1-1-1 boosts burst bandwidth
  • Burst modes fit more processors
  • Auto increment reduces glue logic
  • Byte writes reduce write traffic
  • GW simplifies full-word updates
  • Tri-state OE enables bus sharing
  • ZZ mode lowers standby power
  • 3.135–3.6 V eases power design
  • 2.5/3.3 V I/O eases interfacing

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