CY7C1372KV33-200AXC
Active and preferred
RoHS Compliant
Lead-free

CY7C1372KV33-200AXC

Datasheet
package

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CY7C1372KV33-200AXC
CY7C1372KV33-200AXC
Datasheet


Product details

  • Architecture
    NoBL, Pipeline
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 18
  • Density
    18 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    200 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3.135 V to 3.6 V
  • Organization (X x Y)
    1Mb x 18
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Commercial
  • Read Latency (Cycles)
    2

Recommended
OPN
CY7C1372KV33-200AXC
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1372KV33-200AXC is an 18-Mbit (1M × 18) synchronous pipelined burst SRAM with NoBL architecture for zero wait-state back-to-back reads and writes at 200 MHz. It uses a 3.3 V core supply (VDD 3.135 to 3.6 V) with 3.3 V or 2.5 V I/O (VDDQ 3.135 V to VDD or 2.375 to 2.625 V). Features include registered inputs/outputs, byte write, linear or interleaved burst, ZZ sleep, and IEEE 1149.1 JTAG boundary scan.

Features

  • 250 MHz synchronous burst SRAM
  • Zero wait-state read/write switching
  • No Bus Latency (NoBL) architecture
  • Fully registered I/O for pipelining
  • Clock-to-output tCO 2.5 ns max
  • Burst counter, up to 4 transfers
  • Linear or interleaved burst order
  • Byte write with BWx signals
  • Self-timed synchronous write logic
  • 3 chip enables + async OE tri-state
  • ZZ sleep mode, data retained
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • High throughput at 250 MHz bus
  • Fast turnarounds, no wait states
  • Sustains back-to-back R/W cycles
  • Predictable timing for high-speed
  • 2.5 ns tCO reduces read latency
  • 4-beat bursts reduce addr toggles
  • Burst modes match bus protocols
  • Byte writes cut RMW overhead
  • No write timing tuning needed
  • Easy bank expansion, avoids fights
  • Sleep cuts standby, keeps data
  • JTAG simplifies board test/debug

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