CY7C1372KV25-167AXC
Active and preferred
RoHS Compliant
Lead-free

CY7C1372KV25-167AXC

Data Sheet
package

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CY7C1372KV25-167AXC
CY7C1372KV25-167AXC
Data Sheet

Product details

  • Architecture
    NoBL, Pipeline
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 18
  • Density
    18 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    167 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    2.38 V to 2.63 V
  • Organization (X x Y)
    1Mb x 18
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Commercial
  • Read Latency (Cycles)
    2
Recommended
OPN
CY7C1372KV25-167AXC
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 360
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 360
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1372KV25-167AXC is an 18-Mbit (1M × 18) 2.5 V synchronous pipelined burst SRAM with No Bus Latency (NoBL) architecture. It supports 167 MHz bus operation with fully registered inputs/outputs for zero wait-state back-to-back reads and writes. VDD and VDDQ operate from 2.375 V to 2.625 V. It includes byte-write control, CEN clock suspend, ZZ sleep mode, and IEEE 1149.1 JTAG boundary scan in a 100-pin TQFP Pb-free package.

Features

  • NoBL for zero wait-state R/W
  • 200 MHz synchronous pipelined SRAM
  • 3.2 ns clock-to-output at 200 MHz
  • Fully registered inputs and outputs
  • On-chip burst counter, up to 4 beats
  • Linear or interleaved burst sequence
  • Byte write via BWx byte selects
  • Auto three-state outputs on write
  • 2.375 V to 2.625 V VDD supply
  • VDDQ I/O supply from 2.375 V to VDD
  • CEN clock enable holds internal state
  • ZZ sleep mode; 65 mA standby max

Benefits

  • Zero wait states boost throughput
  • 200 MHz supports fast SRAM buses
  • 3.2 ns tCO reduces read latency
  • Pipelining eases timing closure
  • 4-beat bursts cut address overhead
  • Burst order fits cache line patterns
  • Byte writes simplify RMW updates
  • Auto tri-state avoids bus contention
  • 2.5 V core rail eases power design
  • Separate VDDQ improves I/O matching
  • CEN enables stall without data loss
  • ZZ mode cuts standby power draw

Applications

Documents

Design resources

Partner solutions

Developer community

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