CY7C1370KV33-250AXC
Active and preferred
RoHS Compliant
Lead-free

CY7C1370KV33-250AXC

Datasheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C1370KV33-250AXC
CY7C1370KV33-250AXC
Datasheet


Product details

  • Architecture
    NoBL, Pipeline
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 36
  • Density
    18 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    250 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3.135 V to 3.6 V
  • Organization (X x Y)
    512Kb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Commercial
  • Read Latency (Cycles)
    2

Recommended
OPN
CY7C1370KV33-250AXC
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1370KV33-250AXC is an 18-Mbit (512K × 36) synchronous pipelined burst SRAM with NoBL architecture for 250 MHz, zero-wait-state transfers. It uses registered inputs and outputs with 2.5 ns clock-to-output (tCO). Features include byte writes, linear or interleaved burst up to four words, CEN clock suspend, and ZZ sleep mode. 3.3 V VDD with 3.3 V/2.5 V VDDQ in 100-pin Pb-free TQFP.

Features

  • 250 MHz synchronous burst SRAM
  • Zero wait-state read/write switching
  • No Bus Latency (NoBL) architecture
  • Fully registered I/O for pipelining
  • Clock-to-output tCO 2.5 ns max
  • Burst counter, up to 4 transfers
  • Linear or interleaved burst order
  • Byte write with BWx signals
  • Self-timed synchronous write logic
  • 3 chip enables + async OE tri-state
  • ZZ sleep mode, data retained
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • High throughput at 250 MHz bus
  • Fast turnarounds, no wait states
  • Sustains back-to-back R/W cycles
  • Predictable timing for high-speed
  • 2.5 ns tCO reduces read latency
  • 4-beat bursts reduce addr toggles
  • Burst modes match bus protocols
  • Byte writes cut RMW overhead
  • No write timing tuning needed
  • Easy bank expansion, avoids fights
  • Sleep cuts standby, keeps data
  • JTAG simplifies board test/debug

Applications

Documents

Design resources

Partner solutions

Developer community