CY7C1041GN30-10BVXIT
Active and preferred
RoHS Compliant
Lead-free

CY7C1041GN30-10BVXIT

Data Sheet
package
ea.
in stock

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CY7C1041GN30-10BVXIT
CY7C1041GN30-10BVXIT
ea.
Data Sheet

Product details

  • Density
    4 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    10 ns
Recommended
OPN
CY7C1041GN30-10BVXIT
Product Status active and preferred
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY7C1041GN30-10BVXIT is a 4-Mbit asynchronous SRAM organized as 256K × 16, for parallel memory expansion in embedded systems. It operates from 2.2 V to 3.6 V over -40°C to 85°C (industrial) with 10 ns address access time. Byte writes are supported via BLE/BHE. The 65 nm GN process enables low leakage (ISB2 8 mA max) and 45 mA max ICC, in a 48-ball VFBGA (6 × 8 × 1.0 mm) tape-and-reel package.

Features

  • 4-Mbit SRAM, 256K × 16
  • tAA access time 10 ns / 15 ns
  • 18-bit address bus A0 to A17
  • 16-bit I/O bus I/O0 to I/O15
  • Byte write enables BHE and BLE
  • CE and OE control read, HI-Z
  • Data retention down to 1.0 V
  • VDR = 1 V for data retention
  • tRC read cycle 10 ns / 15 ns
  • tDOE OE to data 4.5 ns / 8 ns
  • Standby current ISB2 6 mA typ
  • Input/output leakage ±1 µA

Benefits

  • Fast 10 ns access cuts latency
  • 16-bit bus boosts throughput
  • Byte writes reduce write traffic
  • HI-Z outputs ease bus sharing
  • 1.0 V retention preserves data
  • Wide VCC options fit many rails
  • Low standby current saves power
  • Low leakage supports low power
  • Simple CE/OE/WE control logic
  • Quick OE access speeds reads
  • Predictable 10/15 ns cycles
  • Stable levels ease interfacing

Applications

Documents

Design resources

Partner solutions

Developer community

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