CY7C1041G30-10ZSXA
Active and preferred
RoHS Compliant
Lead-free

CY7C1041G30-10ZSXA

Datasheet
package

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CY7C1041G30-10ZSXA
CY7C1041G30-10ZSXA
Datasheet


Product details

  • Density
    4 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    256Kb x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Automotive(A)
  • Speed
    10 ns

Recommended
OPN
CY7C1041G30-10ZSXA
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 135
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Est. Longevity Date 2033
Launch Date 03/2022
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 135
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Est. Longevity Date 2033
Launch Date 03/2022
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW
CY7C1041G30-10ZSXA is a 4-Mbit (256K × 16) asynchronous SRAM with embedded ECC for single-bit error correction and AEC-Q100 qualification. It operates from 2.2 V to 3.6 V with 10 ns access time, supports byte writes via BLE/BHE and OE/WE control, and offers low currents (ICC 38 mA typ, ISB2 6 mA typ at 3.6 V). The device is offered in a 44-pin TSOP II package for -40°C to 85°C operation.

Features

  • 4-Mbit SRAM (256K x 16)
  • Embedded ECC single-bit correct
  • tAA address access time 10 ns
  • Read cycle time tRC 10 ns
  • OE to data valid tDOE 4.5 ns
  • Byte write via BHE/BLE controls
  • Dual chip enables CE1/CE2 logic
  • I/O Hi-Z when deselected/disabled
  • VCC operating range 2.2 V to 3.6 V
  • Data retention at 1.0 V
  • ICC 40 mA typ, 50 mA max
  • ISB2 standby 6 mA typ, 14 max

Benefits

  • Fits 16-bit systems, fewer chips
  • Corrects 1-bit errors for integrity
  • 10 ns access cuts read latency
  • 10 ns cycles support fast bus ops
  • 4.5 ns OE speeds async reads
  • Byte writes reduce write bandwidth
  • CE1/CE2 eases bus decoding
  • Hi-Z outputs simplify bus sharing
  • 2.2-3.6 V works with 3.3 V rails
  • 1.0 V retention saves backup power
  • Known ICC helps power budgeting
  • Low standby reduces idle power
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