CY7C1041G30-10BAJXET
Active and preferred
RoHS Compliant

CY7C1041G30-10BAJXET

Datasheet
package

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CY7C1041G30-10BAJXET
CY7C1041G30-10BAJXET
Datasheet


Product details

  • Density
    4 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 125 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Automotive(E)
  • Speed
    10 ns

Recommended
OPN
CY7C1041G30-10BAJXET
Product Status active and preferred
Infineon Package
PG-TFBGA-48
Package Name FBGA-48 (001-85259)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TFBGA-48
Package Name FBGA-48 (001-85259)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1041G30-10BAJXET is an AEC-Q100 qualified 4-Mbit (256K × 16) asynchronous SRAM with embedded ECC for single-bit error correction. It operates from 2.2 V to 3.6 V with 10 ns access time, supports byte writes via BLE/BHE, and provides data retention down to 1.0 V. Automotive-E grade and a Pb-free 48-ball VFBGA package (tape-and-reel) target reliable nonvolatile-like data storage in automotive ECUs.

Features

  • 4-Mbit SRAM (256K x 16)
  • Embedded ECC single-bit correct
  • tAA address access time 10 ns
  • Read cycle time tRC 10 ns
  • OE to data valid tDOE 4.5 ns
  • Byte write via BHE/BLE controls
  • Dual chip enables CE1/CE2 logic
  • I/O Hi-Z when deselected/disabled
  • VCC operating range 2.2 V to 3.6 V
  • Data retention at 1.0 V
  • ICC 40 mA typ, 50 mA max
  • ISB2 standby 6 mA typ, 14 max

Benefits

  • Fits 16-bit systems, fewer chips
  • Corrects 1-bit errors for integrity
  • 10 ns access cuts read latency
  • 10 ns cycles support fast bus ops
  • 4.5 ns OE speeds async reads
  • Byte writes reduce write bandwidth
  • CE1/CE2 eases bus decoding
  • Hi-Z outputs simplify bus sharing
  • 2.2-3.6 V works with 3.3 V rails
  • 1.0 V retention saves backup power
  • Known ICC helps power budgeting
  • Low standby reduces idle power
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