CY62167GN30-45BVXI
Active and preferred
RoHS Compliant
Lead-free

CY62167GN30-45BVXI

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CY62167GN30-45BVXI
CY62167GN30-45BVXI


Product details

  • Density
    16 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    1M x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial

OPN
CY62167GN30-45BVXI
Product Status active and preferred
Infineon Package
Package Name VFBGA-48 (51-85150)
Packing Size 960
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Est. Longevity Date 2033
Launch Date 03/2022
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
TW
Infineon stock last updated:
ea. in stock

Product Status
Active
Infineon Package
Package Name VFBGA-48 (51-85150)
Packing Size 960
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Est. Longevity Date 2033
Launch Date 03/2022
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
TW
CY62167GN30-45BVXI is a 16-Mbit (1M × 16 or 2M × 8) high-performance CMOS SRAM with 45 ns access. It runs from 2.2 V to 3.6 V over -40°C to +85°C and supports easy expansion using CE1, CE2, and OE plus byte enables (BLE/BHE). Automatic power-down cuts standby to 1.5 µA typical (8 µA max); operating ICC is 29 mA typical at 22.22 MHz. BVXI is a Pb-free 48-ball VFBGA (6 × 8 × 1 mm).

Features

  • 16-Mbit SRAM; 1M×16 or 2M×8
  • 45 ns read cycle time (tRC)
  • 22 ns OE to data valid (tDOE)
  • 2.2 V to 3.6 V supply (VCC)
  • 1.5 µA typ standby current (ISB)
  • 8 µA max standby current (ISB1)
  • 35 mA max ICC at 22.22 MHz
  • 1 V data retention supply (VDR)
  • 8 µA max data retention (ICCDR)
  • Byte enables BHE/BLE for 8-bit
  • High-Z I/O via CE/OE/BHE/BLE
  • ESD >2001 V (MIL-STD-883)

Benefits

  • Flexible 16/8-bit bus interface
  • 45 ns access supports fast CPU
  • 22 ns OE improves read latency
  • 2.2–3.6 V fits 3 V systems
  • 1.5 µA standby extends battery
  • 8 µA max limits sleep power
  • 35 mA max reduces active power
  • Retains data down to 1 V VCC
  • µA retention cuts backup power
  • Byte writes cut write energy
  • High-Z enables easy expansion
  • High ESD improves robustness
Documents

Design resources

Developer community