CY62158EV30LL-45ZSXI
Active and preferred
RoHS Compliant
Lead-free

CY62158EV30LL-45ZSXI

Datasheet
package
ea.
in stock

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CY62158EV30LL-45ZSXI
CY62158EV30LL-45ZSXI
ea.
Datasheet


Product details

  • Density
    8 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    1M x 8
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    45 ns

Recommended
OPN
CY62158EV30LL-45ZSXI
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1350
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW,US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1350
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW,US
ea.
in stock
CY62158EV30LL-45ZSXI is an 8-Mbit (1024K × 8) CMOS asynchronous SRAM for low-power portable systems. It operates from 2.2 V to 3.6 V over -40 to +85°C and provides 45 ns access. Automatic power-down when deselected cuts standby to 2 µA typical (8 µA max), while active current is 6 mA typical at 1 MHz. Chip enables CE1/CE2 and OE support read/write control. The -45ZSXI variant is a Pb-free 44-pin TSOP II.

Features

  • 8-Mbit SRAM organized 1024K × 8
  • 45 ns read/write cycle time
  • 22 ns OE to data valid
  • 2.2 V to 3.6 V single supply
  • 6 mA typ active at 1 MHz
  • 18 mA typ at fmax, 25 mA max
  • 2 µA typ standby, 8 µA max
  • Auto power-down when deselected
  • Data retention at VCC ≥ 1.5 V
  • 3.2 µA typ ICCDR, 8 µA max
  • Tri-state outputs with OE control
  • CE1/CE2 chip enable for expansion

Benefits

  • 45 ns cycles reduce access latency
  • 22 ns OE speeds read data access
  • 2.2–3.6 V fits 3.3 V systems
  • 6 mA active extends battery life
  • Low standby cuts sleep-mode drain
  • Auto power-down saves energy idle
  • 1.5 V retention preserves state
  • Tri-state I/O simplifies bus sharing
  • CE1/CE2 enables easy scaling
  • CMOS I/O levels ease MCU interface
  • Low leakage helps data integrity
  • High speed boosts system throughput

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