CY62157G30-45ZXI
Active and preferred
RoHS Compliant
Lead-free

CY62157G30-45ZXI

Data Sheet
package

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CY62157G30-45ZXI
CY62157G30-45ZXI
Data Sheet

Product details

  • Density
    8 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    512K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
Recommended
OPN
CY62157G30-45ZXI
Product Status active and preferred
Infineon Package
PG-TSOP-48
Package Name TSOP-I-48 (51-85183)
Packing Size 96
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TSOP-48
Package Name TSOP-I-48 (51-85183)
Packing Size 96
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY62157G30-45ZXI is an 8-Mbit (512K × 16) CMOS MoBL SRAM with embedded ECC that detects and corrects single-bit errors. The -45 speed grade supports 45 ns access at 2.2 V to 3.6 V and industrial -40°C to +85°C operation, with dual chip enable control (CE1/CE2). Byte writes use BHE/BLE, and the Byte Power Down feature forces standby when both bytes are disabled, with ISB2 typ 1.4 µA and max 6.5 µA.

Features

  • 8-Mbit SRAM (512K × 16)
  • Embedded ECC corrects 1-bit errors
  • ERR pin flags corrected 1-bit errors
  • 45 ns read/write cycle time
  • VCC supply 1.65 V to 3.6 V
  • Standby current 6.5 µA max
  • Data retention at VDR = 1.0 V
  • Dual chip enable inputs (CE1, CE2)
  • Byte writes via BHE/BLE signals
  • Hi-Z outputs when deselected/OE HIGH
  • Byte power-down via BHE & BLE HIGH
  • HBM ESD rating >2001 V

Benefits

  • ECC improves data integrity in SRAM
  • ERR output simplifies error handling
  • 45 ns access supports fast CPUs
  • 1.65–3.6 V fits multi-rail systems
  • 6.5 µA max cuts standby power
  • 1.0 V retention saves backup energy
  • Dual CE supports simple bank select
  • Byte writes reduce bus bandwidth use
  • Hi-Z outputs ease bus sharing
  • Byte power-down saves idle power
  • HBM >2001 V improves robustness
  • Clear timing specs speed validation

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }