CY62148EV30LL-55SXIT
Active and preferred
RoHS Compliant

CY62148EV30LL-55SXIT

Data Sheet
package

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CY62148EV30LL-55SXIT
CY62148EV30LL-55SXIT
Data Sheet

Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    512K x 8
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Speed
    55 ns
Recommended
OPN
CY62148EV30LL-55SXIT
Product Status active and preferred
Infineon Package
PG-DSO-32
Package Name SOIC-32 (51-85081)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-DSO-32
Package Name SOIC-32 (51-85081)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY62148EV30LL-55SXIT is a 4-Mbit (512K × 8) CMOS SRAM for 3 V systems, rated 55 ns access and operating from 2.2 V to 3.6 V over –40°C to +85°C. It supports automatic power-down when CE is HIGH, with standby current 2.5 µA typical (7 µA max) and VCC operating current 3.5 mA typical at 1 MHz or 15 mA typical at fmax. Pb-free 32-pin SOIC, industrial grade, tape-and-reel for portable and embedded memory.

Features

  • 4-Mbit SRAM (512K × 8)
  • 2.2 V to 3.6 V supply
  • 45 ns read cycle time (tRC)
  • 22 ns OE LOW to data valid
  • Auto power-down when CE HIGH
  • Standby current 2.5 µA typ
  • Standby current 7 µA max
  • Active current 3.5 mA at 1 MHz
  • Data retention at VCC = 1.5 V
  • Data retention current 8.8 µA max
  • I/O high-Z when CE/OE HIGH
  • 10 pF max input/output capacitance

Benefits

  • Fast reads reduce CPU wait states
  • Wide VCC fits 3.3 V designs
  • Auto power-down cuts idle power
  • µA standby extends battery life
  • Low active current saves energy
  • 1.5 V retention preserves data
  • High-Z outputs ease bus sharing
  • Low I/O caps support fast edges
  • Quick OE access boosts throughput
  • Simple CE/OE control expands memory
  • Lower heat from low supply current
  • Predictable timings simplify design

Applications

Documents

Design resources

Partner solutions

Developer community

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