CY621472E30LL-45ZSXI
Active and preferred
RoHS Compliant
Lead-free

CY621472E30LL-45ZSXI

Datasheet
package

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CY621472E30LL-45ZSXI
CY621472E30LL-45ZSXI
Datasheet


Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    45 ns

Recommended
OPN
CY621472E30LL-45ZSXI
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 135
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW,US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 135
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW,US
CY621472E30LL-45ZSXI is a 4-Mbit (256K × 16) CMOS SRAM for battery-powered embedded systems. It operates from 2.2 V to 3.6 V over –40°C to +85°C and delivers a 45 ns access time. Typical active current is 3.5 mA at 1 MHz (6 mA max), while standby power-down current is 2.5 µA typical (7 µA max) when deselected. Dual chip enables and byte enables support easy expansion and 8-bit accesses.

Features

  • 256K × 16 CMOS SRAM architecture
  • 45 ns read/write cycle time
  • VCC operating range 2.2 V to 3.6 V
  • 3.5 mA active at 1 MHz (typ)
  • 2.5 µA standby current (typ)
  • Standby cuts power >99% deselect
  • Data retention at VCC = 1.5 V
  • ICCDR 8.8 µA max at VCC = 1.5 V
  • Byte write via BHE/BLE controls
  • Automatic power-down on deselect
  • OE-controlled tri-state outputs

Benefits

  • Fast 45 ns access reduces latency
  • 2.2–3.6 V fits common 3.3 V
  • Low active current extends battery
  • µA standby reduces sleep power
  • Deselect power-down saves energy
  • 1.5 V retention keeps data saved
  • Byte writes cut bus activity
  • Tri-state outputs simplify bus sharing
  • CE1/CE2 supports easy expansion
  • CMOS I/O eases MCU interfacing
  • High-Z outputs reduce contention

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