CY62138FV30LL-45ZXIT
Active and preferred
RoHS Compliant
Lead-free

CY62138FV30LL-45ZXIT

Datasheet
package

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CY62138FV30LL-45ZXIT
CY62138FV30LL-45ZXIT
Datasheet

Product details

  • Density
    2 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    256K x 8
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Speed
    45 ns
Recommended
OPN
CY62138FV30LL-45ZXIT
Product Status active and preferred
Infineon Package
PG-TSOP-32
Package Name TSOP-I-32 (51-85056)
Packing Size 1500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TSOP-32
Package Name TSOP-I-32 (51-85056)
Packing Size 1500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The CY62138FV30LL-45ZXIT is a 2-Mbit (256K × 8) CMOS static RAM for fast parallel data storage, offering 45 ns access and easy memory expansion using CE1, CE2, and OE control. It runs from 2.2 V to 3.6 V over –40°C to 85°C and targets low-power systems with automatic power-down when deselected, 1.6 mA typical active current at 1 MHz, and 1 µA typical standby (5 µA max). Pb-free TSOP I.

Features

  • 2-Mbit SRAM, 256K × 8
  • 45 ns read/write cycle time
  • VCC range 2.2 V to 3.6 V
  • ICC 1.6 mA typ at 1 MHz
  • Standby 1 µA typ, 5 µA max
  • Auto power-down when deselected
  • Data retention at VCC = 1.5 V
  • ICCDR 4 µA max at VCC = 1.5 V
  • 18-bit address bus (A0 to A17)
  • 8-bit bidirectional I/O (I/O0–I/O7)
  • Dual chip enables CE1 and CE2
  • High-Z outputs when deselected

Benefits

  • Fits 8-bit MCU data bus
  • 45 ns supports fast CPU access
  • 2.2–3.6 V matches 3 V rails
  • Low active ICC reduces energy
  • µA standby extends battery life
  • Auto power-down saves idle power
  • 1.5 V retention keeps data in sleep
  • Low ICCDR cuts retention drain
  • 18-bit addr eases memory mapping
  • High-Z outputs prevent bus fights
  • Dual CE and OE simplify expansion
  • Async SRAM interface speeds design

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