CY62138FLL-45SXI
Active and preferred
RoHS Compliant
Lead-free

CY62138FLL-45SXI

Datasheet
package
ea.
in stock

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CY62138FLL-45SXI
CY62138FLL-45SXI
ea.
Datasheet


Product details

  • Density
    2 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    4.5 V to 5.5 V
  • Operating Voltage (VCCQ) max
    5.5 V
  • Organization (X x Y)
    256K x 8
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial
  • Speed
    45 ns

Recommended
OPN
CY62138FLL-45SXI
Product Status active and preferred
Infineon Package
PG-DSO-32
Package Name SOIC-32 (51-85081)
Packing Size 500
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-DSO-32
Package Name SOIC-32 (51-85081)
Packing Size 500
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
ea.
in stock
CY62138FLL-45SXI is a 2-Mbit (256K × 8) high-performance CMOS static RAM with TTL input levels for processor interfaces. It operates from 4.5 V to 5.5 V over -40°C to +85°C and delivers 45 ns access time. Low-power operation includes 1.6 mA typical ICC at 1 MHz (2.5 mA max) and automatic CE power-down standby of 1 µA typical (5 µA max) when deselected. The -45SXI option is a Pb-free 32-pin SOIC.

Features

  • 2-Mbit SRAM, 256K × 8 org
  • 45 ns read/write cycle time
  • 4.5 V to 5.5 V supply (VCC)
  • 1.6 mA typ active at 1 MHz
  • 1 µA typ standby, 5 µA max
  • Automatic power-down via CE
  • 2.0 V data retention supply (VDR)
  • ICCDR 1 µA typ, 5 µA max
  • TTL-compatible input levels
  • Tri-state outputs with OE/CE/WE
  • Input/output leakage ±1 µA
  • ESD > 2001 V (MIL-STD-883)

Benefits

  • Fast 45 ns SRAM lowers wait states
  • Fits 5 V rails in legacy designs
  • Low active current cuts power use
  • µA standby extends battery run time
  • Auto power-down saves idle energy
  • 2.0 V retention prevents data loss
  • Low ICCDR eases backup supply sizing
  • TTL inputs simplify MCU/CPU hookup
  • Tri-state enables shared data bus
  • Low leakage reduces standby losses
  • High ESD improves handling robustness
  • CE/OE control supports expansion

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