CY62136ESL-45ZSXIT
Active and preferred
RoHS Compliant
Lead-free

CY62136ESL-45ZSXIT

Datasheet
package

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CY62136ESL-45ZSXIT
CY62136ESL-45ZSXIT
Datasheet


Product details

  • Density
    2 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 5.5 V
  • Operating Voltage (VCCQ) max
    5.5 V
  • Organization (X x Y)
    128K x 16
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Speed
    45 ns

Recommended
OPN
CY62136ESL-45ZSXIT
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
US
CY62136ESL-45ZSXIT is a 2-Mbit (128 K × 16) CMOS asynchronous SRAM for battery-powered and embedded designs. It supports 45 ns access and operates from 2.2 V to 3.6 V or 4.5 V to 5.5 V VCC (specs not guaranteed from 3.6 V to 4.5 V). With 44-pin Pb-free TSOP II, it interfaces to TTL input levels and provides byte writes via BLE/BHE. Active current is 2.5 mA max at 1 MHz and standby is 7 µA max with automatic CE power-down.

Features

  • 2-Mbit SRAM, 128K × 16
  • 45 ns read/write cycle time
  • VCC: 2.2–3.6 V or 4.5–5.5 V
  • Standby 1 µA typ, 7 µA max
  • Active 2 mA typ @ 1 MHz
  • CE auto power-down current 1 µA
  • Byte write via BLE/BHE enables
  • Tri-state outputs via CE/OE/WE
  • Data retention at VCC = 1.0 V
  • ICCDR 0.8 µA typ, 3 µA max
  • I/O leakage ±1 µA (IIX, IOZ)
  • CIN/COUT max 10 pF

Benefits

  • 128K×16 simplifies parallel buses
  • 45 ns supports fast CPU access
  • 2 supply options ease reuse
  • 7 µA max extends battery standby
  • 2 mA @1 MHz cuts active power
  • Auto power-down saves idle energy
  • Byte writes reduce write bandwidth
  • Tri-state I/O eases bus sharing
  • 1.0 V retention preserves data
  • Low ICCDR reduces backup power
  • Low leakage improves sleep budgets
  • 10 pF I/O eases signal integrity

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