CY23EP09ZXC-1H
not for new design
RoHS Compliant
Lead-free

CY23EP09ZXC-1H

Datasheet
package
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CY23EP09ZXC-1H
CY23EP09ZXC-1H
View product family
Datasheet


Product details

  • Category
    Zero Delay Buffers
  • Core/IO Operating Voltages ((V))
    2.5/3.3
  • Features
    2.5V or 3.3V,10- 220 MHz, Low Jitter, 9 Output Zero Delay Buffer
  • Function
    See datasheet
  • I/O Voltage ((V))
    2.5/3.3
  • Input Frequency range
    10 MHz to 220 MHz
  • Input Type
    LVCMOS/LVTTL
  • Lead Ball Finish
    Ni/Pd/Au
  • On-chip Clock Generation (PLL)
    1
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    2.3 V to 3.6 V
  • Output Frequency range
    10 MHz to 220 MHz
  • Output Signal Type
    LVCMOS
  • Outputs
    9
  • Peak Reflow Temp
    260 °C
  • Publish in NPSG
    N
  • Publish in PSG
    Y
  • Qualification
    Commercial
  • Spread Spectrum
    N

OPN
CY23EP09ZXC-1H
Product Status not for new design
Infineon Package
PG-TSSOP-16
Package Name TSSOP-16 (51-85091)
Packing Size 480
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
US
View product family

Product Status not for new design
Infineon Package
PG-TSSOP-16
Package Name TSSOP-16 (51-85091)
Packing Size 480
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
US
View product family
The CY23EP09ZXC-1 H is a high-drive, nine-output zero delay buffer supporting 2.5 V or 3.3 V operation with input and output frequencies from 10 MHz to 220 MHz. It offers 25 ps cycle-to-cycle jitter, 45 ps typical output-output skew, and zero input-output propagation delay. Featuring an on-chip PLL, LVCMOS/LVTTL inputs, and LVCMOS outputs, it operates from 2.3 V to 3.6 V at 0°C to 70°C in a 16-pin TSSOP.

Features

  • Zero input-output propagation delay
  • 45 ps typical output-output skew
  • 25 ps cycle-to-cycle jitter
  • 15 ps period jitter
  • On-chip PLL with CLKOUT feedback
  • One input drives nine outputs (4+4+1)
  • Selectable output banks, 3-state control
  • Input clock can bypass PLL for test mode
  • Standard and high drive strength options
  • Power-down mode with <25 μA current draw
  • Output impedance: 29–41 Ω (typical)
  • Closed-loop bandwidth up to 1.5 MHz

Benefits

  • Zero delay ensures precise clock
  • 45 ps skew enables tight timing margins
  • 25 ps jitter supports high-speed systems
  • 15 ps period jitter improves signal
  • PLL feedback maintains stable operation
  • Nine outputs simplify clock distribution
  • Selectable banks offer flexible design
  • Test mode eases system validation
  • Drive options match system requirements
  • Power-down mode cuts standby power
  • Low output impedance improves signal
  • Wide bandwidth supports fast clock edges

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