Please note that this is an end of life product. See newer alternative product version Please note that this is an end of life product. See newer alternative product version
END OF LIFE
discontinued
RoHS Compliant
Lead-free

CY14B101KA-SP25XI

END OF LIFE

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CY14B101KA-SP25XI
CY14B101KA-SP25XI

Product details

  • Alarms
    Y
  • Density
    1 MBit
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    3.6 V
  • Operating Voltage range
    2.7 V to 3.6 V
  • Organization (X x Y)
    128Kb x 8
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Real Time Clock
    Y
  • Speed
    25 ns
  • Watchdog Timer
    Y
OPN
CY14B101KA-SP25XI
Product Status discontinued
Infineon Package
Package Name SSOP-48 (51-85061)
Packing Size 300
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status discontinued
Infineon Package
Package Name SSOP-48 (51-85061)
Packing Size 300
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY14B101KA-SP25XI is a 1-Mbit (128K × 8) nvSRAM with integrated real-time clock, combining SRAM with QuantumTrap nonvolatile elements. It supports 25 ns access and automatic STORE on power-down using a small capacitor, with STORE/RECALL also by hardware or software. Operates from 2.7 V to 3.6 V over -40°C to 85°C, rated for 20-year data retention and 1 million STORE cycles to nonvolatile elements.

Features

  • 1-Mbit nvSRAM + QuantumTrap NVM
  • AutoStore on power-down via VCAP
  • Hardware STORE request via HSB pin
  • SW STORE/RECALL via addr sequence
  • Parallel STORE/RECALL of all cells
  • Infinite SRAM reads and writes
  • Infinite RECALL from nonvolatile
  • 1M STORE cycles to QuantumTrap
  • 20-year data retention
  • RTC with leap-year tracking
  • RTC alarm with INT output
  • 0.35 µA typ RTC backup current

Benefits

  • AutoStore saves data on power loss
  • Small cap avoids battery for store
  • HSB pin enables immediate save
  • SW cycles need no extra interface
  • Parallel xfer minimizes save time
  • SRAM-like speed for fast accesses
  • Restore state without wear limits
  • High STORE endurance for logging
  • Long retention reduces servicing
  • Keeps time/date during outages
  • Alarm/INT enables timed wakeups
  • Low backup current extends life

Applications

Documents

Design resources

Developer community

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